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| 32bit tx system risc tx19 family tmp1942cyue TMP1942CZUE/xbg rev1.0 march 29, 2007
tx1942cy/cz tmp1942cy/cz-1 32-bit risc microprocessor tx19 family tmp1942cyue/czue/czxbg 1. outline and features the tx19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit risc solution with the added advantage of a significantly reduce code size of a 16-bit architecture. the instruction set of the tx19 includes as a subset the 32-bit instructions of the tx39, which is based on th e mips r3000a tm architecture. additionally, the tx19 supports the mips16 tm application-specific extensions (ase) for improved code density. the tmp1942 is built on a tx19 core processor and a selection of intelligent peripherals. the tmp1942 is suitable for low-voltage, low-power applications. features of the tmp1942 include the following: restrictions on product use 070122ebp ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality an d reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inher ent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba produc ts are used within specified operating ranges as set forth in the most recent toshiba produc ts specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices, ? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intend ed for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipmen t, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instrument s, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical in struments, all types of safety devices, etc. unintended usage of toshiba products listed in th is document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited und er any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our pr oducts. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers ca n be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions. 030619_s tx1942cy/cz tmp1942cy/cz-2 (1) tx19 core processor 1) two instruction set architecture (isa) modes: 16-bit isa for code density and 32-bit isa for speed ? the 16-bit isa is object-code compatible with the code-efficient mips16 tm ase. ? the 32-bit isa is object-code compatible with the high-performance tx39 family. 2) combines high performance with low power consumption. - high performance ? single clock cycle execution for most instructions ? 3-operand computational instructions for high instruction throughput ? 5-stage pipeline ? on-chip high-speed memory ? dsp function: executes 32-bit x 32-bit multiplier operations with a 64- bit accumulation in a single clock cycle. - low power consumption ? optimized design using a low-power cell library ? programmable standby modes in which processor clocks are stopped 3) fast interrupt response suitable for real-time control ? distinct starting locations for each interrupt service routine ? automatically generated vectors for each interrupt so urce ? automatic updates of the interrupt mask level (2) internal ram: fdue/fdxbg: 20kb,cyue/czue/czxbg: 16 kb internal rom: fdue/fdxbg: 512kb,cyue/czxbg: 384kb,cyue: 256 kb rom correction function (8 words x 4 blocks) (for fdue/fdxbg, only registers are available; data is not replaced.) (3) external memory expansion ? 16-mbyte off-chip address space for code and dat a ? external bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (4) 4-channel dma controller ? interrupt- or software-triggered (5) 6 channel 8-bit pwm timer (12 channel 8-bit interval timer, 6 channel 16-bit interval timer, 6 channel 8-bit ppg output) (6) 14 channel 16-bit timer (2 channels support 2-phase in put pulse counter mode.) (7) 1 channel real-time counter (rtc) (8) 5 channel general-purpose serial interface (supports both uart and synchronous transfer modes) (9) 1 channel serial bus interface either i 2 c bus mode or clock-synchronous mode can be selected. (10) 16 channel 10-bit a/d converter (with internal sample/hold) conversion time: 2 s (throughput), 4 to 5 s (latency) (11) 3 channel 10-bit d/a converter (12) watchdog timer (13) 4 channel chip select/wait controller tx1942cy/cz tmp1942cy/cz-3 (14) interrupt sources ? 4 cpu interrupts: software interrupt instruction ? 45 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt ? 29 external interrupts: 7 priority levels, with the exception of the nmi interrupt the external sources include 14 kwup sources, which are all assigned to a single interrupt vector, and 4 extended in terrupts (intb, intc, intd, and inte), which are all assigned to a single interrupt vector with an identification flag. thus, the actual number of external interrupt sources is 13. (15) 108 pin input/output ports (16) three standby function ? idle, sleep, and stop (17) dual clocks ? rtc clock: low-speed clock (3 2.768 khz) (18) clock generator ? on-chip pll (x4) ? clock gear: divides the operating speed of the cpu by 1/2, 1/4 or 1/8 (19) operating voltage range: 2.7 to 3.6 v pc and pf are 2.7 to 3.6 v or 4.5 to 5.25 v for 5 v-enabled ports. (20) operating frequency ? 32 mh z (vcc 3.0 v) ? 28 mhz (vcc 2.7 v) (21) package ? 144-pin qfp (16 x 16 x 1.4 (t) mm, 0.4-mm pitch): fdue/czue/cyue ? 177-pin csp (13 x 13 x 1.4 (t) mm, 0.8-mm pitch): fdxbg/czxbg note: tmp1942fdxbg (package: 177-pin csp) is under development. tx1942cy/cz tmp1942cy/cz-4 figure 1.1 tmp1942 block diagram dmac (4ch) tx19 proccessor core g-bus intc ebif i/o bus i/f port0 port1 port2 10-bit adc (16ch) sio0 sio1 serial bus i/f port3 port4 wdt real-time counter (rtc) sio4 sio5 8-bit tmr0/1 a/b (12ch) 16-bit tmr0-d (14ch) tx19 cpu mac dsu 256 kbrom ( * ) 16 kbram cg 10-bit dac (3ch) sio3 intbcde kwup nmi int0 (pf6) int1 2 (pe6 7) int3 4 (pa0 1) int5 6 (pa3 4) int7 (pb7) int8 a (pc0 2) an0 7 (p50 57) an8 15 (p60 67) adtrg (p57) avcc/avss daout0 3 davcc/davss darefh txd0 (pd0) rxd0 (pd1) sclk0/cts0 (pd2) txd1 (pd3) rxd1 (pd4) sclk1/cts1 (pd5) txd3 (pe0) rxd3 (pe1) sclk3/cts3 (pe2) vrefh/vrefl sck (pf3) so/sda (pf4) si/scl (pf5) txd4 (pe3) rxd4 (pe4) sclk4/cts4 (pe5) txd5 (pf0) rxd5 (pf1) tb4in1 (pb5), tb0in0 1 (pa0 1) tb7in0 1 (p95 96), tb1in0 1 (pa3 4) tb8in0 1 (pc6 7), tb2in0 1 (pb0 1) tb9in0 1 (pd0 1), tb3in0 1 (pb3 4) tbain0 1 (pd5 6), tb4in0 (pb2) tb0out (pa2), tb4out (p92) tb1out (pa5), tb5out (p93) tb2out (pb2), tb6out (p94) tb3out (pb5), tb7out (p97) ta1out (pa6), ta7out (pc5) ta3out (pb6), ta9out (pc7) ta5out (pc3), tabout (pd5) jtag sclk5/cts5 (pf2) x1 x2 xt1 (pd6) xt2 (pd7) scout (p44) plloff* reset * bw0/1 intlv (pe7) a d0 7 (p00 p07) a d8/a8 ad15/a15 (p10 p17) a 0/a16 a7/a23 (p20 p27) rd (p30) wr (p31) hwr (p32) wait (p33) busrd (p34) busak * (p35) r/w (p36) p37 cs0 cs3 (p40 p43) intb c (pb0 1) intd e (pb3 4) rom correction ( * ) mrom for the mask rom version. czue/xbg:384kb ta0in (pa7), ta6in (pc1 ) ta2in (pb7), ta8in (pc2 ) ta4in (pc0), taain (pc4 ) tx1942cy/cz tmp1942cy/cz-5 2. signal descriptions this section contains pin assignments for the tmp1942 as well as brief descriptions of the functions of the tmp1942 input and output pins. 2.1 pin assignment table 2.1.1 shows tmp1942 pin assignment. figure 2.1.1 144-pin lqfp pin assignment 144 143 142 141 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 140 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 41 11 108 tx1942cy/cz tmp1942cy/cz-6 table 2.1.1 pin assignment (144-pin lqfp) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vrefh 37 p11/ad9/a9 73 p90/key8/dclk 109 cvcc 2 vrefl 38 p12/ad10/a10 74 p91/key9/pcst2 110 x2 3 p50/an0 39 p13/ad11/a11 75 p92/tb4out/pcst1 111 cvss 4 p51/an1 40 p14/ad12/a12 76 p93/tb5out/pcst0 112 x1 5 p52/an2 41 p15/ad13/a13 77 p94/tb6out/sdsa0/tpc 113 test1 6 p53/an3 42 p16/ad14/a14 78 p95/tb7in0/dbge 114 reset 7 davcc 43 p17/ad15/a15 79 p96/tb7in1/dint 115 pd6/xt1 8 davss 44 p20/a0/a16 80 p97/tb7out/dreset 116 pd7/xt2 9 dareh 45 p21/a1/a17 81 dvcc3 117 nmi 10 daout0 46 p22/a2/a18 82 pa0/tb0in0/int3 118 bw0 11 daout1 47 p23/a3/a19 83 pa1/tb0in1/int4 119 pb0/tb2in0/intb 12 daout2 48 p24/a4/a20 84 pa2/tb0out 120 pb1/tb2in1/intc 13 p54/an4 49 p25/a5/a21 85 pa3/tb1in0/int5 121 pb2/tb2out/tb4in0 14 p55/an5 50 p26/a6/a22 86 pa4/tb1in1/int6 122 pb3/tb3in0/intd 15 p56/an6 51 p27/a7/a23 87 pa5/tb1out 123 pb4/tb3in1/inte 16 p57/an7/adtrg 52 test0 88 pa6/ta1out 124 pb5/tb3out/tb4in1 17 p60/an8/key0 53 plloff 89 pa7/ta0in/keya 125 pb6/ta3out 18 dvss 54 dvss 90 dvss 126 dvss 19 p61/an9/key1 55 ale 91 rstpup 127 dvcc3 20 p62/an10/key2 56 dvcc3 92 pc0/ta4in/int8 128 pb7/ta2in/int7/keyb 21 p63/an11/key3 57 bw1 93 pc1/ta6in/int9 129 pd0/txd0/tb9in0 22 p64/an12/key4 58 p30/rd 94 pc2/ta8in/inta 130 pd1/rxd0/tb9in1 23 p65/an13/key5 59 p31/wr 95 pc3/ta5out 131 pd2/sclk0/cts0 24 p66/an14/key6 60 p32/hwr 96 pc4/taain 132 pd3/txd1/tbain0 25 p67/an15/key7 61 p33/wait 97 pc5/ta7out 133 pd4/rxd1/tbain1 26 dvcc3 62 p34/busrq 98 pc6/tb8in0/keyc 134 pd5/sclk1/cts1/tabout 27 p00/ad0 63 p35/busak 99 pc7/tb8in1/ta9out 135 pe0/txd3 28 p01/ad1 64 p36/r/w 100 dvcc52 136 pe1/rxd3 29 p02/ad2 65 p37/dsu 101 pf0/txd5 137 pe2/sclk3/cts3 30 p03/ad3 66 dvss 102 pf1/rxd5/keyd 138 pe3/txd4 31 p04/ad4 67 dvcc3 103 pf2/sclk5/cts5 139 pe4/rxd4 32 p05/ad5 68 p40/cs0 104 pf3/sck 140 pe5/sclk4/cts4 33 p06/ad6 69 p41/cs1 105 pf4/so/sda 141 pe6/int1/boot 34 p07/ad7 70 p42/cs2 106 pf5/si/scl 142 pe7/int2/intlv 35 dvss 71 p43/cs3 107 pf6/int0 143 avcc 36 p10/ad8/a8 72 p44/scout 108 dvcc51 144 avss tx1942cy/cz figure 2.1.2 shows pin assignment for the 177-pin model of the tmp1942. a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 e1 e2 e3 e4 e12 e13 e14 e15 f1 f2 f3 f4 f12 f13 f14 f15 g1 g2 g3 g4 g12 g13 g14 g15 h1 h2 h3 h4 h12 h13 h14 h15 j1 j2 j3 j4 j12 j13 j14 j15 k1 k2 k3 k4 k12 k13 k14 k15 l1 l2 l3 l4 l12 l13 l14 l15 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 figure 2.1.2 177-pin csp pin assignment tmp1942cy/cz-7 tx1942cy/cz tmp1942cy/cz-8 table 2.1.2 pin assignment (177-pin csp) pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 vrefl d1 p50/an0 h13 nc n4 p16/ad14/a14 a2 avss d2 davss h14 nc n5 p21/a1/a17 a3 avcc d3 p52/an2 h15 dvss n6 p25/a5/a21 a4 pe7/int2/intlv d4 p51/an1 j1 p67/an15/key7 n7 dvss a5 pe3/txd4 d5 pe0/txd3 j2 p65/an13/key5 n8 test0 a6 tck (jtag) d6 pd3/txd1/tbain0 j3 p66/an14/key6 n9 p30/rd a7 pd2/sclk0/cts0 d7 pb7/ta2in/int7/keyb j4 p64/an12/key4 n10 p32/hwr a8 pb5/tb3out/tb4in1 d8 dvss j12 pa6/ta1out n11 p37 a9 pb1/tb2in1/intc d9 pb2/tb2out/ tb4in0 j13 pa7/ta0in/keya n12 dvss a10 pd7/tx2 d10 nmi j14 nc n13 p41/cs1 a11 pd6/tx1 d11 nc j15 pa5/tb1out n14 p91/key9 a12 x1 d12 nc k1 p01/ad1 n15 nc a13 x2 d13 pf1/rxd5/keyd k2 dvcc3 p1 nc a14 cvcc d14 pf3/sck k3 nc p2 p10/ad8/a8 a15 nc d15 pf6/int0 k4 nc p3 p12/ad10/a10 b1 nc e1 davcc k12 pa2/tb0out p4 p20/a0/a16 b2 nc e2 daout0 k13 pa3/tb1in0/int5 p5 p22/a2/a18 b3 pe6/int1 e3 darefh k14 pa4/tb1in1/int6 p6 p26/a6/a22 b4 pe4/rxd4 e4 p53/an3 k15 pa1/tb0in1/int4 p7 tdo (jtag) b5 trst (jtag) e5 nc (bonding not applied) l1 p04/ad4 p8 ale b6 pd5/sclk1/cts1/tabout e12 pc6/tb8in0/keyc l2 p02/ad2 p9 bw1 b7 pd0/txd0/tb9in0 e13 dvcc52 l3 tms (jtag) p10 p33/wait b8 dvcc3 e14 pf0/txd5 l4 p00/ad0 p11 tdi (jtag) b9 pb4/tb3in1/inte e15 pf2/sclk5/cts5 l12 p97/tb7out p12 p40/cs0 b10 pb0/tb2in0/intb f1 daout1 l13 dvcc3 p13 p42/cs2 b11 nc f2 p55/an5 l14 pa0/tb0in0/int3 p14 p44/scout b12 reset f3 p54/an4 l15 p96/tb7in1 p15 nc b13 cvss f4 daout2 m1 p07/ad7 r1 p11/ad9/a9 b14 dvcc51 f12 pc2/ta8in/inta m2 p05/ad5 r2 nc b15 nc f13 pc4/taain m3 p03/ad3 r3 nc c1 vrefh f14 pc5/ta7out m4 p14/ad12/a12 r4 p13/ad11/a11 c2 nc f15 pc7/tb8in1/ta9out m5 p15/ad13/a13 r5 p17/ad15/a15 c3 pe5/sclk4/cts4 g1 p56/an6 m6 p24/a4/a20 r6 p23/a3/a19 c4 pe2/sclk3/cts3 g2 p61/an9/key1 m7 plloff r7 p27/a7/a23 c5 pe1/rxd3 g3 nc m8 nc r8 nc c6 pd4/rxd1/tbain1 g4 p60/an8/key0 m9 dvcc3 r9 p31/wr c7 pd1/rxd0/tb9in1 g12 pc0/ta4in/int8 m10 p34/busrq r10 p35/busak c8 pb6/ta3out g13 pc1/ta6in/int9 m11 p36/r/w r11 dvcc3 c9 pb3/tb3in0/intd g14 nc m12 p93/tb5out r12 nc c10 bw0 g15 pc3/ta5out m13 p94/tb6out r13 p43/cs3 c11 nc h1 dvss m14 p95/tb7in0 r14 nc c12 test1 h2 p63/an11/key3 m15 p92/tb4out r15 p90/key8 c13 pf4/so/sda h3 p57/an7/adtrg n1 nc c14 pf5/si/scl h4 p62/an10/key2 n2 dvss c15 nc h12 rstpup n3 p06/ad6 tx1942cy/cz 2.2 pin usage information table 2.2.1 lists the names and functions of the tmp1942?s input/output pins. table 2.2.1 pin names and functions pin name # of pins type function p00~p07 ad0~ad7 8 input/output input/output port 0: individually programmable as input or output address (lower): bits 0-7 of the address/data bus p10~p17 ad8~ad15 a8~a15 8 input/output input/output output port 1: individually programmable as input or output address/data (upper): bits 8-15 of the address/data bus address: bits 8-15 of the address bus p20~p27 a0~a7 a16~a23 8 input/output output output port 2: individually programmable as input or output address: bits 0-7 of the address bus address: bits 16-23 of the address bus p30 rd 1 output output port 30: output-only read strobe: asserted during a read operation from an external memory device p31 wr 1 output output port 31: output-only write strobe: asserted during a write operation on d0-d7 p32 hwr 1 input/output output port 32: programmable as input or output (with internal pull-up resister) higher write strobe: asserted during a write operation on d8-d15 p33 wait 1 input/output input port 33: programmable as input or output (with internal pull-up resister) wait: causes the cpu to sus pend external bus activity p34 busrq 1 input/output input port 34: programmable as input or output (with internal pull-up resister) bus request: asserted by an external bus master to request bus mastership p35 busak 1 input/output output port 35: programmable as input or output (with internal pull-up resister) bus acknowledge: indicates that the cp u has relinquished the bus in response to busrq . p36 r/w 1 input/output output port 36: programmable as input or output (with internal pull-up resister) read/write: indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle p37 dsu 1 input/output input port 37: programmable as input or output (with internal pull-up resister) this pin is used to select the operating mode during reset. the tmp1940cyaf enters normal mode when this pin is sa mpled high at the rising edge of reset . this pin should not be pulled down to a logic 0 dur ing a reset sequence. the tmp1940fdbf, which has an on-chip flash, uses this pin as an interface to the dsu tool. for details, refer to part 4, tmp1940fdbf . p40 cs0 1 input/output output port 40: programmable as input or output (with internal pull-up resister) chip select 0: asserted low to enable external devices at programmed addresses p41 cs1 1 input/output output port 41: programmable as input or output (with internal pull-up resister) chip select 1: asserted low to enable external devices at programmed addresses p42 cs2 1 input/output output port 42: programmable as input or output (with internal pull-up resister) chip select 2: asserted low to enable external devices at programmed addresses p43 cs3 1 input/output output port 43: programmable as input or output (with internal pull-up resister) chip select 3: asserted low to enable external devices at programmed addresses p44 scout 1 input/output output port 44: programmable as input or output system clock output: drives out a cloc k signal at the same frequency as the cpu clock (high-speed or low-speed) p50~p57 an0~an7 adtrg 8 input input input port 5: input-only analog input: input to the a/d converter external start request for the a/d converter (multiplexed with p57) p60~p67 an8~an15 key0-key7 1 input/output input output port 6: input-only analog input: input to the a/d converter key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) p90 dsu (dclk) key8 1 input/output output input port 90: programmable as input or output dsu pin key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) tmp1942cy/cz-9 tx1942cy/cz tmp1942cy/cz-10 pin name # of pins type function p91 dsu (pcst2) key9 1 input/output output input port 91: programmable as input or output dsu pin key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) p92 dsu (pcst1) tb40ut 1 input/output output output port 92: programmable as input or output dsu pin 16-bit timer 4 output: output from 16-bit timer 4 p93 dsu (pcst0) tb5out 1 input/output output output port 93: programmable as input or output dsu pin 16-bit timer 5 output: output from 16-bit timer 5 p94 dsu (sdsa0/tpc) tb6out 1 input/output output output port 94: programmable as input or output dsu pin 16-bit timer 6 output: output from 16-bit timer 6 p95 dsu (dbge * ) tb7in0 1 input/output input port 95: programmable as input or output dsu pin 16-bit timer 7 input 0: count/captur e trigger input to 16-bit timer 7 p96 dsu (dint * ) tb7in1 1 input/output input port 96: programmable as input or output dsu pin 16-bit timer 7 input 1: capture trigger input to 16-bit timer 7 p97 dsu (dreset) tb7out 1 input/output input output port 97: programmable as input or output dsu pin 16-bit timer 7 output: output from 16-bit timer 7 pa0 tb0in0 int3 1 input/output input input port a0: programmable as input or output 16-bit timer 0 input 0: count/capture trigger input to 16-bit timer 0 interrupt request 3: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pa1 tb0in1 int4 1 input/output input input port a1: programmable as input or output 16-bit timer 0 input 1: capture trigger input to 16-bit timer 0 interrupt request 4: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pa2 tb0out 1 input/output output port a2: programmable as input or output 16-bit timer 0 output: output from 16-bit timer 0 pa3 tb1in0 int5 1 input/output input input port a3: programmable as input or output 16-bit timer 1 input 0: count/capture trigger input to 16-bit timer 1 interrupt request 5: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pa4 tb1in1 int6 1 input/output input input port a4: programmable as input or output 16-bit timer 1 input 1: capture trigger input to 16-bit timer 1 interrupt request 6: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pa5 tb1out 1 input/output output port a5: programmable as input or output 16-bit timer 1 output: output from 16-bit timer 1 pa6 ta1out 1 input/output output port a6: programmable as input or output 8-bit timer 0/1 output: output from 8-bit timer 0 or 1 pa7 ta0in keya 1 input/output input input port a7: programmable as input or output 8-bit timer 0 input: input to 8-bit timer 0 key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) pb0 tb2in0 intb 1 input/output input input port b0: programmable as input or output 16-bit timer 2 input 0: count/capture trigger input/2-phase input pulse counter input to 16-bit timer 2 interrupt request b: programmable to be high-level, low-level, rising-edge or falling-edge sensitive tx1942cy/cz pin name # of pins type function pb1 tb2in1 intc 1 input/output input input port b1: programmable as input or output 16-bit timer 2 input 1: capture trigger inpu t/2-phase input pulse counter input to 16-bit timer 2 interrupt request c: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb2 tb2out tb4in0 1 input/output output input port b2: programmable as input or output 16-bit timer 2 output: output from 16-bit timer 2 16-bit timer 4 input 0: count/captur e trigger input to 16-bit timer 4 pb3 tb3in0 intd 1 input/output input input port b3: programmable as input or output 16-bit timer 3 input 0: count/capture trigger input/2-phase input pulse counter input to 16-bit timer 3 interrupt request d: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb4 tb3in1 inte 1 input/output input input port b4: programmable as input or output 16-bit timer 3 input 1: capture trigger inpu t/2-phase input pulse counter input to 16-bit timer 3 interrupt request e: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb5 tb3out tb4in1 1 input/output output input port b5: programmable as input or output 16-bit timer 3 output: output from 16-bit timer 3 16-bit timer 4 input 1: capture trigger input to 16-bit timer 4 pb6 ta3out 1 input/output output port b6: programmable as input or output 8-bit timer 2/3 output: output from 8-bit timer 2 or 3 pb7 ta2in int7 keyb 1 input/output input input input port b7: programmable as input or output 8-bit timer 2 input: input to 8-bit timer 2 interrupt request 7: programmable to be high-level, low-level, rising-edge or falling-edge sensitive key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) pc0 ta4in int8 1 input/output input input port c0: programmable as input or output 8-bit timer 4 input: input to 8-bit timer 4 interrupt request 8: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pc1 ta6in int9 1 input/output input input port c1: programmable as input or output 8-bit timer 6 input: input to 8-bit timer 6 interrupt request 9: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pc2 ta8in inta 1 input/output input input port c2: programmable as input or output 8-bit timer 8 input: input to 8-bit timer 8 interrupt request a: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pc3 ta5out 1 input/output output port c3: programmable as input or output 8-bit timer 4/5 output: output from 8-bit timer 4 or 5 pc4 taain 1 input/output input port c4: programmable as input or output 8-bit timer a input: input to 8-bit timer a pc5 ta7out 1 input/output output port c5: programmable as input or output 8-bit timer 6/7 output: output from 8-bit timer 6 or 7 pc6 tb8in0 keyc 1 input/output input input port c6: programmable as input or output 16-bit timer 8 input 0: count/captur e trigger input to 16-bit timer 8 key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) pc7 tb8in1 ta9out 1 input/output input output port c7: programmable as input or output 16-bit timer 8 input 1: capture trigger input to 16-bit timer 8 8-bit timer 8/9 output: output from 8-bit timer 8 or 9 pd0 txd0 tb9in0 1 input/output output input port d0: programmable as input or output serial transmit data 0 programmable as an open-drain output 16-bit timer 9 input 0: count/captur e trigger input to 16-bit timer 9 tmp1942cy/cz-11 tx1942cy/cz tmp1942cy/cz-12 pin name # of pins type function pd1 rxd0 tb9in1 1 input/output input input port d1: programmable as input or output serial receive data 0 16-bit timer 9 input 1: capture trigger input to 16-bit timer 9 pd2 sclk0 cts0 * 1 input/output input/output input port d2: programmable as input or output serial clock input/output 0 serial clear-to-send 0 programmable as an open-drain output pd3 txd1 tbain0 1 input/output output input port d3: programmable as input or output serial transmit data 1 programmable as an open-drain output 16-bit timer a input 0: count/captur e trigger input to 16-bit timer a pd4 rxd1 tbain1 1 input/output input input port d4: programmable as input or output serial receive data 1 16-bit timer a input 1: capture trigger input to 16-bit timer a pd5 sclk1 cts1 tabout 1 input/output input/output input output port d5: programmable as input or output serial clock input/output 1 serial clear-to-send 1 programmable as an open-drain output 8-bit timer a/b output: output from 8-bit timer a or b pd6 xt1 1 input/output input port d6: programmable as input or open-drain output connection pin for a low-speed crystal pd7 xt2 1 input/output output port d7: programmable as input or open-drain output connection pin for a low-speed crystal pe0 txd3 1 input/output output port e0: programmable as input or output serial transmit data 3 programmable as an open-drain output pe1 rxd3 1 input/output input port e1: programmable as input or output serial receive data 3 pe2 cts3 * 1 input/output input/output input port e2: programmable as input or output serial clock input/output 3 serial clear-to-send 3 programmable as an open-drain output pe3 txd4 1 input/output output port e3: programmable as input or output serial transmit data 4 programmable as an open-drain output pe4 rxd4 1 input/output input port e4: programmable as input or output serial receive data 4 pe5 sclk4 cts4 1 input/output input/output input port e5: programmable as input or output serial clock input/output 4 serial clear-to-send 4 programmable as an open-drain output pe6 int1 boot 1 input/output input port e6: programmable as input or output interrupt request 1: individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. single-boot mode setting pin: used when rewrit ing built-in flash memory (low active). during normal operation, this pin should be pulled up. this pin should always be pulled up for the mask rom version. pe7 int2 intlv 1 input/output input port e7: programmable as input or output interrupt request 2: individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. interleave mode setting pin: th is pin should be pulled up w hen using interleave mode. otherwise, it should be pulled down. pf0 txd5 1 input/output output port f0: programmable as input or output serial transmit data 5 programmable as an open-drain output tx1942cy/cz tmp1942cy/cz-13 pin name # of pins type function pf1 rxd5 keyd 1 input/output input input port f1: programmable as input or output serial receive data 5 key on wake-up input (with internal pull- up resister) (dynamic pull-up selectable) pf2 sclk5 cts5 1 input/output input/output input port f2: programmable as input or output serial clock input/output 5 serial clear-to-send 5 programmable as an open-drain output pf3 sck 1 input/output input/output port f3: programmable as input or output clock input/output pin when the serial bus interface is in sio mode pf4 so sda 1 input/output output input/output port f4: programmable as input or output data transmission pin when the serial bus interface is in sio mode data transmission/reception pin when t he serial bus interface is in i 2 c mode programmable as an open-drain output pf5 si scl 1 input/output input input/output port f5: programmable as input or output data reception pin when the serial bus interface is in sio mode clock input/output pin when the se rial bus interface is in i 2 c mode programmable as an open-drain output pf6 int0 input/output input port f6: programmable as input or output interrupt request 0: individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. ale 1 output address latch enable (this signal is driven out only when external memory is accessed) test0 1 input test pin test1 1 input test pin rstpup 1 input when this pin is driven high (upon reset), pull-up for ports 3 and 4 is enabled. when this pin is driven low, pull-up is disabled. daout0-2 3 output d/a converter output nmi 1 input non-maskable interrupt request: causes an nmi interrupt on the falling edge bw0~1 2 input set both am0 and am1 to 1. plloff 1 input this pin should be tied to logic 1 when the frequency multiplied clock from the pll is used; otherwise, it should be tied to logic 0. reset 1 input reset (with internal pull-up resister): initializes the whole tmp1940cyaf vrefh 1 input input pin for high reference voltage for the a/d converter. vrefl 1 input input pin for low reference voltage for the a/d converter. avcc 1 ? power supply pin for the a/d converter. th is pin should always be connected to power supply even when the a/d converter is not used. avss 1 ? ground pin for the a/d converter. this pi n should always be connected to ground even when the a/d converter is not used. davcc 1 ? power supply pin for the d/a converter. th is pin should always be connected to power supply even when the d/a converter is not used. davss 1 ? ground pin for the d/a converter. this pi n should always be connected to ground even when the d/a converter is not used. darefh 1 ? reference voltage input pin for the d/a converter x1/x2 2 input/output resonator connecting pin cvcc 1 ? power supply pin for the oscillator cvss 1 ? ground pin for the oscillator (0 v) dvcc3 4 ? power supply pins dvcc51 1 ? power supply pin (port f) dvcc52 1 ? power supply pin (port c) dvss 5 ? ground pins (0 v) port c becomes a 5 v port when a 5 v power supply is connected to dvcc52. port f becomes a 5 v port when a 5 v power supply is connected to dvcc51. note: when the dsu is enabled, port 9 functions as the processor probe interfacing signal regardless of the setting of the port 9 control register (p9cr). tx1942cy/cz tmp1942cy/cz-14 the following table lists the jtag specific pins added to the csp package: pin name # of pins type function trst 1 input jtag reset pin (with internal pull-up resistor) tck 1 input jtag clock pin (with internal pull-up resistor) tdi 1 input jtag data input pin (with internal pull-up resistor) tdo 1 output jtag data output pin tms 1 input jtag mode switching input pin (with internal pull-up resistor) tmp1942cy/cz tmp1942cy/cz-15 3. functional description this section describes the functions and basic operation of each individual circuit bl ock in the tmp1942 series devices . 3.1 processor core the tx1942 contains a high - performance 32 - bit processor core ( the tx19 processor core ). for details of the operation of the processor core , refer to ? tx19 family architecture ?. functions unique to the tmp1942 , which are not explained in ? tx19 family architecture ?, are described below . 3.1.1 reset operation to reset the tmp1942 , reset must be input low ( at 0 ) for at least 12 system clock cycles while the power supply voltage is within the rated operating range and the internal high - frequency oscillator is oscillating stably . ( with the device operating at 32 mhz , this period is equal to 3 s if the pll is being used and 6 s if the pll is not being used .) after a reset the pll - multiplied clock is specified by the setting of the plloff pin and the clock gear is initialized to 1 / 8 mode . to reset the tmp1942 , reset must be asserted for at least 12 system clock periods after the power supply voltage and the internal high - frequency oscillator have stabilized . this time is typically 3 s at 32 mhz when the on - chip pll is utilized , and 6 s otherwise . after a reset , either the pll - multiplied clock or an external clock is selected , depending on the logic state of the plloff pin . by default , the selected clock is geared down to 1 / 8 for internal operation . the following occurs as a result of a reset : ? the system control coprocessor ( cp0 ) registers within the tx19 core processor are initialized . for details , refer to the architecture manual . ? the reset exception is taken . program control is transferred to the exception handler at a predefined address . this predefined location is called an exception vector , which directly indicates the start of the actual exception handler routine . the reset exception is always vectored to virtual address 0xbfc0 _ 0000 ( which is the same as for the nonmaskable interrupt exception ). ? all on - chip i / o peripheral registers are initialized . ? all port pins , including those multiplexed with on - chip peripheral functions , are configured as either general - purpose inputs or general - purpose outputs . recommended power-on sequence: in powering up this device, it is reco mmended that the dvcc3 be turned on first. at power-on, the pull-up resistor s and input & output buffers pull-down resistors attached to the i/o ports of the 5v supply domain may rail become unstable or a through current may pass through the port until the dv cc3 has stabilized, when an in jection order is not kept. tmp1942cy/cz tmp1942cy/cz-16 3.2 memory map figure 3.2.1 shows a memory map of the tmp1942 . figure 3.2.1 memory map note 1: the internal rom is mapped into the memory spac e from 0x1fc0_0000 to 0x1fc3_ffff (for a 256-kb rom) or 0x1fc0_0000 to 0x1fc5_ffff (for a 384-kb rom). the in ternal ram is mapped into the memory space from 0xffff_8000 to 0xffff_bfff (for a 16-kb ram). note 2: the memory space from 0xffff_4000 to 0xffff_bfff is a reserved ram area. any area other than those shown above, where physical memory is located, should not be accessed. note 3: the internal memory data is stored in conti guous physical address locations starting at 0x1fc0_0000. if exception vector addresses are placed in internal rom, the system control coprocessor (cp0) status register's bev bit must be set to 1 (the default). (this is because exception vector addresses are dispersed if bev = 0.) if memory is added externally, the bev bit can be set to 0. however, since a virtual address space of 0x0000_0000 32 kb is easier to access for reasons of code efficiency, this area is reflected in the contiguous physic al address space from 0x4000_0000 upwards (as indicated by the shaded area) which corresponds to a virtual address space starting at 0x0000_0000 and which is equal in size to the internal memory. hence, accessing this area is equivalent to accessing the internal memory. example: using 32-bit isa ? access to the 0x0000_0000 32 kb area addiu r2, r0, 7 ; r 2 (0x0000_0007) sw r2, io (_t) (r0) ; 0x0000_xxxx (r2) can be accessed using a single instruction. ? access to areas other than 0x0000_0000 32 kb lui r3, hi (_f) ; upper address is set to r3. addiu r2, r0, 8 ; r2 (0x0000_0008) sw r2, io (_f) (r3) ; memory is accessed after lower address has been set. note 4: the tx1942 supports access to only 16 mbytes of physical space as external address space. a 16-mbyte physical address space can be placed in any chip-select area within the cpu's 3.5 gbytes of physical address space. however, when access to the internal memory, internal i/o space or a reserved area is performed, the external address space cannot be accessed simultaneously, since the other types of access have priority. note 5: do not place an instruction in the last four words of the physical area. ? the relevant area of the internal rom is 0x1fc3_fff0 to 0x1fc3_ffff (for a 256-kb rom) or 0x1fc5_fff0 to 0x1fc5_ffff (for a 384-kb rom). ? if rom is added externally, this restriction applies to the last four words of the installed memory (system-dependent). internal rom area reflected 0xffff_ffff virtual address 16 mbytes reserved kseg1 (uncacheable) kseg2 (cacheable) 16 mbytes reserved kseg0 (cacheable) kuseg (cacheable) 0xff00_0000 0xc000_0000 0xbfc0_0000 0xa000_0000 0x8000_0000 0x0007_ffff 0x0000_0000 physical address kseg2 (1 gbyte) cannot be accessed internal rom 512 mbytes internal i/o (reserved) internal ram (16kb) reserved for debugging (2 mb) user program area exception vector area 0xffff_e000 0xffff_afff 0xffff_7000 (reserved) 0xff3f_ffff 0x4003_ffff 0x4000_0000 0x1fc3_ffff 0x1fc0_0000 0xff20_0000 (reserved) maskable interrupt area 0xff00_0000 0x1fc3_ffff 0x1fc0_0400 0x1fc0_0000 16 mbytes reserved 16 mbytes reserved kuseg (2gbyte) tmp1942cy/cz tmp1942cy/cz-17 3.3 clock/standby control there are essentially two modes of clock operation : single - clock mode ( which uses only the x1 and x2 pins ) and dual - clock mode ( which uses the x1 and x2 pins as well as the xt1 and xt2 pins ). figure 3.3.1 shows the state transition dia g ram for each operation mode . (a) state transition in single-clock mode note 1: before transition to slow/sleep mode can occur, the low-speed oscillator (fs) must be oscillating stably. note 2: when sleep mode is terminated, the device returns to the state in which it was placed before entering sleep mode. note 3: the state to which the device returns when stop mode is terminated can be specified us ing system control register syscr0. (b) state transition in dual-clock mode figure 3.3.1 state transition diagrams for different modes figure 3.3.32 default states when the pll is used and those when the pll is not used fosc : clock frequency input via x1 and x2 pins fs : clock frequency input via xt1 and xt2 pins fpll: clock frequency multiplied ( x4 ) by pll fc : clock frequency selected by setting of plloff pin fgear : clock frequency selected by syscr1 < gear1 : gear0 > system clock fsys : clock frequency selected by syscr1 < sysck > fperiph : input clock for peripheral i / o prescaler reset reset terminated idle mode (cpu halted) (i/o select operation) instruction interrupt normal mode (fc/gear value) instruction interrupt stop mode (all circuits turned off) reset reset terminated idle mode (cpu halted) (i/o select operation) instruction interrupt normal mode (fc/gear value) instruction stop mode (all circuits turned off) slow mode (fs) instruction instruction interrupt interrupt instruction instruction interrupt sleep mode (fc only) (only real-time clock timer operating) interrupt reset reset normal mode fc fpll fosc u 4 fsys fc/8 ? fsys fosc/2 fperiph fsys normal mode fc fosc/2 fsys fc/8 ? fsys fosc/16 fperiph fsys a. when a clock generated by the pll is used b. when the pll is not used reset terminated plloff pin (high) pll clock used reset terminated plloff pin (low) pll not used tmp1942cy/cz tmp1942cy/cz-18 3.3.1 block diagram of clock circuits 1. main system clock ? a crystal can be connected between x1 and x2 , or x1 can be externally driven with a clock . ? plloff the on - chip pll can be enabled or disabled ( bypassed ) during reset by using the plloff pin . when the pll is enabled , the input clock frequency is multiplied by four . ? the clock gear can be programmed to divide the clock by 2 , 4 or 8 . ( the default is 1 / 8 on reset .) ? input clock frequency input frequency range fmax fmin pllon (for both resonator and external input) 5~8 (mhz) 32 mhz 2.5 mhz resonator 16~20 (mhz) 20 mhz 1 mhz 16~20 (mhz) 20 mhz 1 mhz plloff external input 20 32 (mhz) 16 mhz *1 1.25 mhz * 1 . syscr1 tmp1942cy/cz tmp1942cy/cz-19 3. block diagram note 1: when using the clock gear to reduce the system clock frequency, make sure that tn of the prescaler output for each peripheral i/o block satisfies the following relationship: tn tmp1942cy/cz tmp1942cy/cz-20 3.3.2 clock generator (cg) registers (1) clock - related registers 7 6 5 4 3 2 1 0 syscr0 bit symbol xen xten rxen rxten rsysck wuef prck1 prck0 (0xffff_ee00) read/write r/w after reset 1 0 1 0 0 0 0 0 function high-speed oscillator 0: turned off 1: oscillating low-speed oscillator 0: turned off 1: oscillating high-speed oscillator after exit from stop mode 0: turned off 1: oscillating low-speed oscillator after exit from stop mode 0: turned off 1: oscillating clock selection after exit from stop mode 0: high speed 1: low speed oscillator warm-up timer (wup) control write 0: don't care write 1: wup start read 0: wup finished read 1: wup operating prescaler clock selection 00: fperiph/4 01: fperiph/2 10: fperiph 11: (reserved) 15 14 13 12 11 10 9 8 syscr1 bit symbol sysck fpsel dfosc gear1 gear0 (0xffff_ee01) read/write r/w r/w after reset - - 0 0 0 - 1 1 function system clock selection 0: high speed (fc) 1: low speed (fs) fperiph selection 0: fgear 1: fc high-speed oscillator frequency division selection 0: divide by 2 1: divide by 1 high-speed clock (fc) gear selection 00: fc 01: fc/2 10: fc/4 11: fc/8 23 22 21 20 19 18 17 16 syscr2 bit symbol drvosch drvoscl wupt1 wupt0 stby1 stby0 drve (0xffff_ee02) read/write r/w - r/w after reset 0 0 1 0 1 1 - 0 function high-speed oscillator driving capability control 0: normal 1: weak low-speed oscillator driving capability control 0: normal 1: weak oscillator warm-up time selection 00: 2 2 /input frequency 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency standby mode selection 00: reserved 01: stop mode 10: sleep mode 11: idle mode 1: pins are also driven in stop mode. 31 30 29 28 27 26 25 24 syscr3 bit symbol scosel alesel lupfg luptm (0xffff_ee03) read/write - r/w - r/w - - r r/w after reset - 0 - 1 - - 0 0 function scout output selection 0: fs 1: fsys ale output width selection 0: fsys 0.5 1: fsys 1.5 lock-up flag 0: lup finished 1: lup in operation lock-up time selection 0: 2 16 /input frequency 1: 2 12 /input frequency tmp1942cy/cz tmp1942cy/cz-21 note 1: standby mode selection depends on the settings of the doze and halt bits in the cp0's internal config register. if the halt bit = 1, the dev ice will enter the mode selected by stby[1:0]. if the doze bit = 1, the device will always enter idle mode. note 2: when the pll is not used, set the luptm bit in the syscr3 register to 1 (i.e., select 2 12 /input frequency). note3: the wurt1-wupt0 bitys in the syscr2 must be not be change d during the oscillator warm-up event ( e.g. sleep-normal-sleep) note 4: do as follows to change the operating mode immediately after the device has warmed up from the clock stop state (e.g., from sleep mode to normal mode to sleep mode). ? warming up by hardware (1) moving from stop or sleep mode to normal mode 1) when the pll is used before moving to the next operating mode, ensu re that the lock-up bit, lupfg, in the syscr3 register has been cleared to zero and wait for five or more instructions to complete (including the instruction to check the lupfg flag). 2) when the pll is not used ? when the oscillator warm - up time (syscr2 < wupt1 : 0>) is programmed as ?01? (i . e ., 2 8 / input frequency ). before moving to the next operating mode , ensure that the lock - up bit , lupfg , in the syscr3 register has been cleared to zero and wait for fi ve or more instructions to complete . ? when the oscillator warm -up time (syscr2 < wupt1 : 0>) is programmed as ? 10? (2 14 / input frequency ) or ?11 ? (2 16 / input frequency ). before moving to the next operating mode , wait for five or more instructions to complete . (2) moving from stop or sleep mode to slow mode it is possible to move to slow mode immediately after the device has warmed up from stop or sleep mode. ? warming up by software (1) moving from slow mode to normal mode 1) when the pll is used it is possible to move to normal mode immediately after the device has warmed up. however, to move to another mode after that, ens ure that the lock-up bit, lupfg, in the syscr3 register has been cleared to zero and wait for five or more instructions to complete (including the instruction to check the lupfg flag). 2) when the pll is not used ? when the oscillator warm - up time (syscr2 < wupt1 : 0>) is programmed as ?01? (i . e ., 2 8 / input frequency ). it is possible to move to normal mode i mmediately after the device has warmed up . however , to move to another mode after that , ensure that the lock -up bit , lupfg , in the syscr3 register has been cleared to zero and wait for five or more instructions to complete . ? when the oscillator warm - up time ( syscr2 < wupt1 : 0 >) is programmed as ? 10 ? ( 2 14 / input frequency ) or ? 11 ? ( 2 16 / input frequency ). it is possible to move to normal mode immediately after the device has warmed up . however , to move to another mode after that , wait for five or more instructions to complete . (2) moving from normal mode to slow mode before moving to slow mode, ensure that the warm-up end flag (i.e., the wuef bit in the syscr0 register) is cleared and wait for five or more instructions to complete. tmp1942cy/cz tmp1942cy/cz-22 (2) standby ( stop / sleep mode ) termination interrupts 7 6 5 4 3 2 1 0 imcga0 bit symbol emcg01 emcg00 int0en (0xffff_ee10) read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function active state setting for int0 standby termination request 00: low level 01: high level 10: falling edge 11: rising edge i n t 0 request input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg11 emcg10 dfosc int1en read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function active state setting for int1 standby termination request 00: low level 01: high level 10: falling edge 11: rising edge i n t 1 request input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg21 emcg20 int2en read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function active state setting for int2 standby termination request 00: low level 01: high level 10: falling edge 11: rising edge int2 request input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg31 emcg30 int3en read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function active state setting for int3 standby termination request 00: low level 01: high level 10: falling edge 11: rising edge i n t 3 request input 0: disable 1: enable tmp1942cy/cz tmp1942cy/cz-23 7 6 5 4 3 2 1 0 imcgb0 bit symbol emcg41 emcg40 int4en (0xffff_ee14) read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function active state setting for int4 standby termination request 00: low level 01: high level 10: falling edge 11: rising edge i n t 4 request input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg51 emcg50 kwupen read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function these bits should always be set to 01. kwup request input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg61 emcg60 intbcdeen read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function these bits should always be set to 01. intbcde request input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg71 emcg70 intrtcen read/write ? ? r/w ? ? ? r/w after reset ? ? 1 0 ? ? ? 0 function these bits s hould always be set to 11. intrtcen request input 0: disable 1: enable tmp1942cy/cz tmp1942cy/cz-24 note 1: when enabling an interrupt source as a means of terminating a standby mode, always set the active state for the corresponding interrupt request. note 2: when using an interrupt, always perform the following steps in order: (1) enable the input for the interrupt if the corresponding pin is also used for a general-purpose port or any other purpose. (2) set the active state for the interrupt during initialization. (3) clear the interrupt request. (4) enable the interrupt. note 3: the tmp1942 has eight interrupt sour ces (int0~int4, intrtc, intb/intc/intd/inte, and kwup0-kwupd) which can be used as a means of te rminating a standby mode. for int0 to int4, use the cg block to specify whether they are us ed to terminate a standby mode and to specify their active edge or level. for intb /intc/intd/inte and kwup 0-kwupd, use the cg block to specify whether they are used to terminate a standby mode and use intbcdest and kwupstn, respectively, to specify their active edge or level. set the active state for the corresponding interrupt source to high in the intc block. example: enable the int0 interrupt imcga0 tmp1942cy/cz tmp1942cy/cz-25 (3) interrupt request clear register 7 6 5 4 3 2 1 0 eicrcg bit symbol icrcg2 icrcg1 icrcg0 (0xffff_ee20) read/write ? ? ? ? ? w after reset ? ? 1 0 ? ? ? ? function clear interrupt request 000: int0 100: int4 001: int1 101:kwup 010: int2 110: intb/c/d/e 011: int3 111: intrtc note : to clear any of the eight interrupt source s which are used for terminating a standby mode: (1) for kwup, use kwupclr. (2) for extended interrupts in tb/intc/intd/inte, use intflg. (3) for int0 to int4 and intrtc, perform the clearing operation twice, first in the cg block and then in the intc block. (4) for all other interrupt sources, use the intc block. 3.3.3 system clock control unit when reset , the device enters single - clock mode with the result that xen = 1 , xten = 0 and gear1 : 0 = 11 ; the system clock fsys is set to fc / 8 (= fc 1 / 8 ). ( since the pll multiplies the original oscillation frequency by 4 , fc equals to fosc 4 , where fosc is the original oscillation frequency .) for example , if the x1 and x2 pins are connected to an 8 - mhz resonator , a reset will set fsys to 4 mhz (= 8 mhz 4 1 / 8 ). to disable the system from using a pll - multiplied clock as the system clock by default , drive the plloff pin low . in this case , too , the system clock fsys will be set to fc / 8 (= fc 1 / 8 ) by a reset . however , since syscr1 < dfosc > is initialized to 0 by a reset ( so that fc = fosc 1 / 2 ), if the x1 and x2 pins are connected to a 25 - mhz resonator , fsys will be 1 . 25 mhz . also , if the device is clocked by an external oscillator and no internal resonator is connected , fc = fosc can be selected by setting syscr1 < dfocs > to 1 after a reset , so that the system clock frequen cy fsys is twice the frequency obtained with an internal resonator . (1) oscillation settling time ( switchover between normal and slow modes ) if a resonator is connected to the resonator - connecting pins , the device uses the built - in warm - up timer to check whether resonator oscillation has settled . the warm - up time can be set to suit the characteristics of the resonator using syscr2 < wupt1 : wupt0 >. the value of syscr0 < wuef > must be checked in software ( using instructions ) to determine the start and completion of the warm - up time . t able 3.3.1 shows warm - up times for m ode switching . tmp1942cy/cz tmp1942cy/cz-26 note 1: warm-up is unnece ssary when the clock generato r uses an oscillator so that its oscillation is stable. note 2: since the warm-up timer is clocked by an oscillati ng clock, it will not be exact if the oscillation frequency fluctuates. the warm-up time should, therefore, be considered to be an approximate value. note 3: before starting the warm-up timer, firs t confirm that the pll lock-up flag tmp1942cy/cz tmp1942cy/cz-27 (3) reducing the driving capability of oscillators if a resonator is connected to the resonator - connecting pins of an oscillator , this function can suppress oscillation noise output from the oscillator , while reducing power consumption by the oscillator . setting syscr2 < drvosch > to 1 causes the driving capability of the high - speed oscillator to degrade ( weak ). similarly , setting syscr2 < drvoscl > to 1 causes the driving capability of the low - speed oscillator to degrade ( weak ). because both bits are initialized to 0 upon a system reset , both oscillators start oscillating with their normal driving capability ( normal ) when the power is turned on . the oscillators must be placed in the normal state (< drvoscl > or < drvosch > = 0 ) when they start oscillating in any other cases, such as when stop / sleep mode is terminated . 1) reducing the driving capab ility of the high-speed oscillator 2) reducing the driving capab ility of the low-speed oscillator 3.3.4 prescaler clock control unit the internal i / o blocks ( tmra01 to tmraab , tmrb0 to tmrbd , sio0 to sio5 , sbi , and adc ) each incorporate a prescaler for dividing the clock frequency . the clock t0 fed into these prescalers is derived from the clock fperiph . fperiph is either fgear or fc ( as specified by the value of syscr1 < fpsel >) divided by either 4 or 2 , or not divided ( as specified by the value of syscr0 < prck1 : prck0 >. by default , fperiph is set to fgear and t0 to fperiph / 4 . 3.3.5 clock multiplication circuit (pll) this circuit multiplies the high - speed oscillator output clock , fosc , by 4 and outputs the result as the clock fpll . this enables the oscillator to yield a fast internal clock with a low oscillator frequency . the pll is halted by a reset . to use the pll , hold the plloff pin high when terminating a reset . note: if a reset is terminated while the plloff pin is held low, the pll will not work and the internal clock chosen will be the original oscillating clock (i.e., it will not be multiplied by 4). resonator c2 c1 oscillation enable x1 pin syscr2 tmp1942cy/cz tmp1942cy/cz-28 since the pll is configur ed as an analog circuit , it requires a certain settling time ( a lock - up time ) after it has been activated , as does the oscillator . the same timer is used for both warm - up and lock - up. the lock - up time must be set using syscr3 < luptm > so that it satisfies the following relationship : lock - up time warm - up time by default , the lock - up time is 2 16 / input frequency . the lock - up timer is initiated as the high - speed oscillator starts warm - up, and the lock - up flag syscr3 < luptm > remains 1 until the pll is locked in phase and cleared to 0 upon the completion of lock - up . if, for example , the pll gets out of lock in a standby mode and control which depends on the software's execution speed , such as real - time processing , is to be performed , the software must check the lock - up flag after operation has started ( i . e ., after warm - up has been completed ) to ensure that the clock has settled , before it starts processing . on the other hand , various hardware settings and static processing , such as register and memory initialization , can be executed before the lock - up flag has been cleared . note: the lupfg bit is undefined when the plloff pin is low (the pll is not used). precautions to be observed when switching clock gear : clock gear switchover is performed by writing a value to syscr1 < gear1 : gear0 >. the clock gear is not switched immediately after the write : a execution time equal to several clock cycles is required . therefore , one or more instructions following the clock gear switchover instruction may be executed using the old clock gear value . if these instructions need to be executed using the new clock gear value , insert a dummy instruction ( which executes a write cycle only ) after the clock gear switchover instruction . when using a clock gear , make sure that the prescaler output tn in each peripheral i / o block satisfies the following relationship : tn < fsys / 2 for this purpose set the clock - related registers so that tn is slower than fsys / 2 . 3.3.6 standby control unit if the halt bit in the tx19 processor core's config register is set in normal mode , the device enters one of the standby modes - idle , sleep or stop - as determined by the contents of syscr2 < stby1 : stby0 >. if the config register's doze bit is set , the device enters idle mode regardless of the setting of syscr2 < stby1 : stby0 >. features of the idle , sleep and stop modes are described below . 1 ) idle : in this mode , only the cpu stops . in the register corresponding to each module there is an idle mode run / stop setup bit for internal i / o . this allows each module to be set independently to run or stop while the device is in idle mode . table 3.3.3 lists the idle setup registers available for each internal i / o m odul e . tmp1942cy/cz tmp1942cy/cz-29 table 3.3.3 idle mode internal i/o setup registers internal i/o idle mode setup register tmra01 ta01run tmp1942cy/cz tmp1942cy/cz-30 (1) operating status in each mode table 3.3.4 operating status in each mode operation mode operating status normal the tx19 processor core and peripheral i/o both operate at the maximum frequency. idle (halt) the tx19 processor core, intc, timer fo r real-time clock, wdt, 2-phase pulse input counter, kwup (dynamic pull-up), pio, and ebif operate with the low-speed clock. idle (doze) processor operation stops and peripheral i/o operate s as specified. sleep processor operation stops. only the internal low-speed oscillator, timer for real-time clock, 2-phase pulse input counter, and kwup (dynamic pull-up) operate (fs). stop processor and peripheral i/o operation stops completely. (2) cg operation in each mode table 3.3.5 cg status in each operating mode clock source mode oscillator pll clock supply to peripheral i/o clock supply to the cpu normal slow u partially supplied (note) idle (halt) selectable u idle (doze) selectable u sleep fs only u timer for real-time clock, 2-phase pulse input counter, and dynamic pull-up u resonator stop u u u u normal u slow u u partially supplied(note) idle (halt) u selectable u idle (doze) u selectable u sleep u u timer for real-time clock, 2-phase pulse input counter, and dynamic pull-up u external input stop u u u u note: this includes the intc, ebif (external bus interface), i/o ports, wdt, and timer for real-time clock. (3) operation of circuit blocks in each mode ( : operating , u : idle ) table 3.3.6 circuit block operating status in each mode circuit block clock source idle (doze) idle (halt) sleep stop tx19 processor core dmac intc ebif external bus right pio da u u u u u u u u u u u (*1) u u u u u u u (*1) adc sio i2c timer counter wdt fsys u u u u u u u u u u 2-phase pulse input counter fsys/fs can be selected to run or stop for each module independently. (fs only) u dynamic pull-up fs u timer for real-time clock fs u cg u *1: dac output is controlled with the op bit for each channel. tmp1942cy/cz tmp1942cy/cz-31 (4) terminating a standby mode the device can be freed from a standby mode by an interrupt request or a reset . the combination of the interrupt mask register < cmask15 : 13 > setting and the current standby mode determines which interrupt source will be used to terminate the standby mode . the interrupt mask register is part of the status register in the tx19 pro cessor core's system control coprocessor ( cp0 ). details are given in table 3.3.7 . ? t e rmination by an interrupt request the operation performed when the device is released from a standby mode by an interrupt request varies according to the interrupt enable status . if the interrupt level which was set before the device entered the standby mode is greater than or equal to the value in the interrupt mask register , the processor services the requested interrupt after exiting the standby mode and then begins executing instructions starting with the one following the instruction to enter the standby mode ( i . e ., the instruction which specified the ap propriate config register bit ). if the interrupt request level is less than the value in the interrupt mask register , the processor immediately begins executing instructions starting with the one following the instruction to enter the standby mode ( i . e ., the instruction which specified the appropriat e config register bit ) without servicing the requested interrupt . ( the interrupt request flag remains 1 .) non - maskable interrupts are always serviced after standby mode has terminated , irrespective of the value of the mask register . ? termination by a reset the device can be released from any standby mode by a reset . however , after release from stop mode , a certain reset time is required for oscillator operation to settle . the reset selects a warm - up time of 2 14 / oscillation frequency . after release by a reset , the internal ram data can be retain ed in the state in which it was placed immediately before the standby mode was entered ; however , all other settings will be initialized . ( after released by an interrupt , other settings are also retained in the state in which they were placed immediately before the standby mode was entered .) table 3.3.7 standby termination source s and standby termination operation interrupt acceptance state interrupt enabled (interrupt level) > (interrupt mask) interrupt enabled (interrupt level) (interrupt mask) standby mode idle (programmable) sleep stop idle (programmable) sleep stop nmi *1 intwdt int0~4, intb~e kwup0~d *1 *1 *1 *1 intrtc int5~a intta0~b inttb0~d (*2) (*2) interrupt intrx0~5, tx0~5 ints2 intad/adhp/adm standby mode termination source reset : after exiting the standby mode, the processor starts servicing the inte rrupt. (reset initializes the lsi.) : after exiting the standby mode, the processor begins executing instructions starting with the one following the instruction to enter the stan dby mode, without servicing the interrupt. tmp1942cy/cz tmp1942cy/cz-32 : cannot be used to exit from a standby mode. *1: the device is actually released from the st andby mode after the warm-up time has passed. *2: only inttb2 and inttb3 can be used when 2-phase pulse input counter mode is selected. note 1: when using a level-sensitive interrupt to te rminate a standby mode, be sure to hold the level until the processor starts servicing the interrupt. if the le vel is changed before that time, the interrupt cannot be serviced properly. note 2: if the interrupts are disabled in the cpu, use the interrupt controller (intc) to disable only the interrupts other than those used for terminating st andby, before placing the device in any of the standby modes. (5) stop mode in stop mode all internal circuits , including the internal oscillator , stop operating . the pin state in stop mode varies according to the setting of syscr2 < drve >, as shown in table 3 . 3 . 10 . once released from stop mode , the device waits for a while ( until the warm - up time ends ) before starting to output the system clock ; the warm - up time is counted by the warm - up counter . this delay is to ensure that the internal oscillator settles properly . after exiting stop mode the device starts operating according to the settings of syscro < rxen , rxten , rsysck >, which select the operating mode ( normal mode or slow mode ) to be entered on exit from stop mode . these settings must be made before the instruction to enter standby mode is executed . the warm - up time is determined by the setting of syscr2 < wupt1 : wupt0 >. (6) timing of terminating stop / sleep mode 1 ) operation mode transition from normal through stop to normal when fosc = 8 mhz w-up time selection syscr2 tmp1942cy/cz tmp1942cy/cz-33 2 ) operation mode transition from normal through sleep to normal when fosc = 8 mhz w-up time selection syscr2 tmp1942cy/cz tmp1942cy/cz-34 table 3.3.8 pin states in stop mode (1/2) pins input/output tmp1942cy/cz tmp1942cy/cz-35 pins input/output tmp1942cy/cz tmp1942cy/cz-36 3.4 interrupts interrupts are controlled by the status < cmask15 : 13> and status < iec > settings in the cp0 status register , as well as by the internal interrupt controller and the cg . for related information , refer to section 5 , ? exception handling ? in ? tx19 family architecture ?. interrupts in the tmp1942 have the following features : ? interrupts from the cpu itself ( software interrupt instructions ): 4 sources ? external interrupt pins ( nmi , int0 - inte , kwup0 - kwupd ): 30 sources ? interrupts from internal i / o : 46 sources ? vector generation for each interrupt source ? 7 interrupt priority levels for each source ? can be used to activate the dmac tmp1942cy/cz tmp1942cy/cz-37 note 1: standby termination is performed via the cg detection ci rcuit. since its output is a high- level active signal, the intc must be set to accept a high -level active signal. note 2: the cg is bypassed for any processing other than standby te rmination. in that case, the active conditions for int0 to i nt4 must be set in the intc. note 3: intrtc requires cg settings for both standby terminat ion and other processing. the intc must be set to accept a high-level active signal. note 4: kwup and intb to intd require se ttings in each circuit block for both standby termination and other processing. the int c must be set to accept a high-level active signal. figure 3.44.1 interrupt connection diagram intnen standby termination control 8 detection circuit high or low level/edge setting high level 8 active high level 7 high or low level/edge setting disable/enable each key input kwup extended interrupts int0 4 5 key0 d intb e active high level rtc 1 1 cg other interrupts intc core high level high level 8 active high level high or low level/edge setting disable/enable input for each interrupt source tmp1942cy/cz tmp1942cy/cz-38 (1) external interrupts int0 to int4 , intb to inte , kwup0 to kwupd , and intrtc 1 ) int0 to int4 when used to terminate a standby mode , these interrupts must have their active state set ( using imcgxx < emcgxx >) and must be enabled for input ( using imcgxx < intxen >) in the cg block . then the active state of each of the in terrupt source must be set to high ( by setting imcxx < eimxx > to 01 ) in the intc block . when these interrupts are not us ed to terminate a standby mode , set their active state in the intc block . 2 ) intb to inte when used to terminate a standby mode , these interrupts must have their active state set to high ( by setting imcgb2 < 21 : 20 > to 10 ) and must be enabled for input ( by setting imcgb2 < 16 > to 1 ) in the cg block . then the active state of each of the interrupt source must be set to high ( by setting imcxx < eimxx > to 01 ) in the intc block . use intnst for each interrupt source to set the active state and enable or disable the interrupt . when these interrupts are not used to terminate a standby mode , make necessary settings in the intc block and in tnst without having to make settings in the cg . 3 ) kw u p0 to kwupd when used to terminate a standby mode , these interrupts must have their active state set to high ( by setting imcgb1 < 21 : 20 > to 10 ) and must be enabled for input ( by setting imcgb1 < 16 > to 1 ) in the cg block . then the active state of each of the interrupt source must be set to high ( by setting imcxx < eimxx > to 01 ) in the intc block . use kwupstn for each interr upt source to set the active state and enable or disable the interrupt . when these interrupts are not used to terminate a standby mode , make necessary settings in the intc block and kwupstn without having to make settings in the cg . 4 ) intrtc regardless of whether intrtc is used to terminate a standby mode , this interrupt must have its active state set to a rising edge ( by setting imcgb3 < 29 : 28 > to 11 ) and must be enabled for input ( by setting imcgb3< 24 > to 1 ) in the cg block . then the active state of each of the interrupt source must be set to high ( by setting imcxx < eimxx > to 01 ) in the intc block . tmp1942cy/cz tmp1942cy/cz-39 (2) external interrupts int5 to inta and internal interrupt signals ( other than intrtc ) all these interrupts must be set in the intc block . the intc resolves priority conflicts between interr upt sources and notifies the tx19 processor core of the interrupt with the highest priority . interrupt register to be set usable interrupt detection level int0 int4, intrtc* imcgx reg.in cg imcx reg.in intc when used to terminate a standby mode, the interrupt source active state must be set to high in the intc block. the active state of these interrupts must be selected in the cg. however, when these interrupts are not used to terminate a standby mode, their active state must be selected in the intc block. in both cases, low level, high level, falling edge and rising edge are all acceptable. intb inte imcgx reg.in cg imcx reg.in intc intnst the interrupt source active state must always be set to high in the intc block. when these interrupts are used to terminate a standby mode, the interrupt source active state must also be set to high in the cg. the active state of these interrupts must be selected in intnst. however, when these interrupts are not used to terminate a standby mode, settings in the cg are not necessary. in both cases, low level, high level, falling edge and rising edge are all acceptable. kwup0 d imcgx reg.in cg imcx reg.in intc kwupstn the interrupt source active state must always be set to high in the intc block. when these interrupts are used to terminate a standby mode, the interrupt source active state must also be set to high in the cg. the active state of these interrupts must be selected in kwupstn. however, when these interrupts are not used to terminate a standby mode, settings in the cg are not necessary. in both cases, low level, high level, falling edge and rising edge are all acceptable. int5 inta imcx reg.in intc low level, high level, falling edge and rising edge are all acceptable in the intc. internal i/o intdman imcx reg.in intc falling edge others imcx reg.in intc rising edge note 1: interrupt level 0 indicates that the corresponding interrupt is disabled. note 2: only a rising edge can be used for intrtc. ? example interrupt settings when int0 is used to request the termination of stop / sleep mode ( falling edge ) a . enabling the interrupt imcga0 < emcg01 : 00> = ? 10 ? : select falling edge for int0 eicrcg < icrcg2 : 0 > = ? 000 ? : clear interrupt request for int0 cg block imcga0 < int0en > = ? 1 ? : enable request input for int0 imc0l < eim11 : 10 > = ? 01 ? : select high level for int0 intclr < eiclr5 : 0 > = ? 000001 ? : clear interrupt request for int0 intc block imc0l < il12 : 10 > = ? 101 ? : set in terrup t level to 5 status < iec > = ? 1 ?, < cmask> = ? xxx ? tx19 processor core b . disabling the interrupt status < iec > = ? 0 ? tx19 processor core imc0l < il12 : 10 > = ? 000 ? : disable interrupt for int0 intclr < eiclr5 : 0 > = ? 000001 ? : clear interrupt request for int0 imcga0 < int0en > = ? 0 ? : disable request input for int0 eicrcg < icrcg2 : 0 > = ? 000 ? : clear interrupt request for int0 intc block cg block tmp1942cy/cz tmp1942cy/cz-40 3.4.1 interrupt sources (1) reset and non - maskable interrupts : reset , nmi and intwdt ( watchdog timer interrupt ) vector address : 0xbfc0 _ 0000 ( virtual address ) (2) maskable interrupts : software and hardware interrupts vector addresses : 0xbfc0 _ 0210 ( virtual address ) to 0xbfc0 _ 0260 ( virtual address ) interrupt source vector a ddress (virtual address) reset non-maskable 0xbfc0_0000 software swi0 0xbfc0_0210 swi1 0xbfc0_0220 swi2 0xbfc0_0230 swi3 0xbfc0_0240 maskable hardware 0xbfc0_0260 note 1: when vector addresses are located in the on-chip rom, set the bev bit in the system control coprocessor (cp0) status register to 1. note 2: maskable software interrupts are generated by setting tmp1942cy/cz tmp1942cy/cz-41 table 3.44.1 hardware interrupt sources interrupt number ivr[9 : 0] interrupt source interrupt control register address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 000 010 020 030 040 050 060 070 080 090 0a0 0b0 0c0 0d0 0e0 0f0 100 110 120 130 140 150 160 170 180 190 1a0 1b0 1c0 1d0 1e0 1f0 200 210 220 230 240 250 260 270 280 290 2a0 2b0 2c0 2d0 2e0 2f0 300 310 320 330 340 350 360 370 380 390 3a0 3b0 3c0 3d0 3e0 3f0 software set int0 pin (standby termination) int1 pin (standby termination) int2 pin (standby termination) int3 pin (standby termination) int4 pin (standby termination) kwup (standby termination) intb/c/d/e pin (standby termination) reserved reserved int5 pin int6 pin int7 pin int8 pin int9 pin int a pin intrx0: serial reception (channel 0) inttx0: serial trans mission (channel 0) intrx1: serial reception (channel 1) inttx1: serial trans mission (channel 1) ints2: serial channel 2 interrupt intrx3: serial reception (channel 3) inttx3: serial trans mission (channel 3) intadhp: highest-priority a/d conversion completed intadm: a/d conversion monitor interrupt intta0: 8-bit timer 0 intta1: 8-bit timer 1 intta2: 8-bit timer 2 intta3: 8-bit timer 3 inttb0: 16-bit timer 0 inttb1: 16-bit timer 1 intrx4: serial reception (channel 4) inttx4: serial trans mission (channel 4) intrx5: serial reception (channel 5) inttx5: serial trans mission (channel 5) reserved reserved intta4: 8-bit timer 4 intta5: 8-bit timer 5 intta6: 8-bit timer 6 intta7: 8-bit timer 7 intta8: 8-bit timer 8 intta9: 8-bit timer 9 inttaa: 8-bit timer a inttab: 8-bit timer b inttba: 16-bit timer a inttbb: 16-bit timer b inttbc: 16-bit timer c inttbd: 16-bit timer d inttb2: 16-bit timer 2 inttb3: 16-bit timer 3 inttb4: 16-bit timer 4 inttb5: 16-bit timer 5 inttb6: 16-bit timer 6 inttb7: 16-bit timer 7 inttb8: 16-bit timer 8 inttb9: 16-bit timer 9 reserved intrtc: interrupt from timer for real-time clock intad: a/d conversion completed intdma0: dma transfer completed (channel 0) intdma1: dma transfer completed (channel 1) intdma2: dma transfer completed (channel 2) intdma3: dma transfer completed (channel 3) imc0l imc0h imc1l imc1h imc2l imc2h imc3l imc3h imc4l imc4h imc5l imc5h imc6l imc6h imc7l imc7h imc8l imc8h imc9l imc9h imcal imcah imcbl imcbh imccl imcch imcdl imcdh imcel imceh imcfl imcfh 0xf f ff_e000 0xffff_e002 0xffff_e004 0xffff_e006 0xffff_e008 0xffff_e00a 0xffff_e00c 0xffff_e00e 0xffff_e010 0xffff_e012 0xffff_e014 0xffff_e016 0xffff_e018 0xffff_e01a 0xffff_e01c 0xffff_e01e 0xffff_e020 0xffff_e022 0xffff_e024 0xffff_e026 0xffff_e028 0xffff_e02a 0xffff_e02c 0xffff_e02e 0xffff_e030 0xffff_e032 0xffff_e034 0xffff_e036 0xffff_e038 0xffff_e03a 0xffff_e03c 0xffff_e03e tmp1942cy/cz tmp1942cy/cz-42 3.4.2 interrupt detection when using interrupts to terminate a standby mode , the following settings are necessary according to the interrupt type : interrupts int0 to int4 have their active state set using the emcgxx field in the cg's internal imcgxx register , then the eimxx field in the intc's internal imcx register is set to high . extended interrupts intb to inte have their active state set to high using the emcg field in the cg's internal imcgb2 register , then the eimxx field in the intc's internal imcx register is set to high . in addition , intnst is used to set the active st ate for each interrupt source and enable / disable the interrupt source. kwup0 to kwupd have their active state set to hi gh using the emcg field in the cg's internal imcgb1 register , then the eimxx field in the intc's internal imcx register is set to high . in addition , kwupstn is used to set the active stat e for each interrupt source and enable / disable the interrupt source . the rtc interrupt has its active state set to a rising edge using the emcgxx field in the cg's internal imcgxx register , then the eimxx field in the intc's internal imcx register is set to high . other interrupts have their active state set using only the eimxx field in the intc's internal imcx register . the active state can be one of the following four : rising edge , falling edge , high level or low level . when the tmp1942 detection circuit recognizes the active st ate of an interrupt request set in this way , it notifies the processor core or the intc of the interrupt request . when the above interrupts are not used to terminate a standby mode , settings in the cg are not required : int0 to int4 require only settings in the intc , intb to inte require the same settings in the intc as for standby termination as well as setting in intnst , and kwup0 to kwupd require the sa me settings in the intc as for standby termination as well as setting in kwupstn . cancellation of interrupt signals is carried out by the interrupt handler after it has recognized the requested interrupt . intb to inte are can celed by reading intflg . interrupt signals from int0 to int4 and intrtc are cancelled by writing the appropriate value to the icrcg field in the cg's internal eicrcg register and then writing the corresponding value to the eiclr field in the intc's internal intclr register . kwup0 to kwupd are canceled by setting kw u pclr . other interrupt signals are canceled by writing the appropriate value to the eiclr field in the intc's internal intclr register . these cancellation procedures apply regardless of whether the active state is an edge or level . tmp1942cy/cz tmp1942cy/cz-43 * the intrtc interrupt must have its active state set to a rising edge in the cg even when it is not used for standby termination. figure 3.44.2 flow for setting external interrupts note: each stage must be completed in the following sequence: set the active level, clear the interrupt request, and then enable the interrupt. ( example of setting int0 for standby termination ) imcga0 < emcg01 : 00> = ? 10 ? : select falling edge for int0 eicrcg < icrcg2 : 0 > = ? 000 ? : clear interrupt request for int0c g block imcga0 < int0en > = ? 1 ? : enable request input for int0 imc0l < eim11 : 10 > = ? 01 ? : select high level for int0 intclr < eiclr5 : 0 > = ? 000001 ? : clear interrupt request for int0 intc block imc0l < il12 : 10 > = ? 101 ? : set in terrup t level to 5 status < iec > = ? 1 ?, < cmask> = ? xxx ? tx19 processor core set intc set kwupstn or intnst set cg set intc (high level) set kwupstn or intnst set cg (high level) set intc (high level) no yes int0 a/ intrtc* intb e kwup0 d int0 4 intrtc intb e kwup0 d start standby termination interrupt? interrupt? set intc (high level) end tmp1942cy/cz tmp1942cy/cz-44 3.4.3 resolving interrupt priority (1) seven interrupt priority levels the tmp1942 has seven interrupt priority levels ; thus for each interrupt source the priority can be set to one of seven levels . the interrupt mode control register ( imcx ) is used for setting interrupt levels . this register includes a 3 - bit level - setting field ( ilx ). the greater the value ( interrupt level ) set in imc < ilx2 : ilx0 >, the higher the interrupt priority . if the value set for an interrupt source in this field is 000 ( i . e ., the interrupt level is set to 0 ), no interrupt is generated for that interrupt source . (2) notification of the interrupt level when an interrupt occurs , the intc notifies the tx19 processor core of the priority level of the interrupt . the tx19 processor core recognizes the interrup t level by reading the il field in the cause register . if multiple interrupts ( with different priority levels ) occur simultaneously , the tx19 processor core is notified of the interrupt with the highest priority . (3) interrupt vector ( notification of interrupt source ) when an interrupt occurs , the intc also sets the vector for the source of the generated interrupt in the vector register ( ivr ). the tx19 processor core reads the vector register to determine the interrupt source . if multiple interrupts ( with the same priority level ) occur simultaneously , the tx19 processor core is notified of th e vector for the interr upt source with the smallest request number . whe n there are no interrupt sources for which an interrupt has occurred , the ivr [ 9 : 4 ] field is 0 . when it is time for the tx19 processor co re to read the vector register value , the intc notifies the processor core . the processor core sets the status < cmask > bit with the interrupt level which it reads . tmp1942cy/cz tmp1942cy/cz-45 3.4.4 intc registers table 3.44.2 intc register map address register symbol register corresponding interrupt number 0xffff_e060 intclr interrupt request clear control all (63 ? 0) 0xffff_e040 ivr interrupt vector register all (63 ? 0) 0xffff_e03c imcf interrupt mode control register f 63 ? 60 0xffff_e038 imce interrupt mode control register e 59 ? 56 0xffff_e034 imcd interrupt mode control register d 55 ? 52 0xffff_e030 imcc interrupt mode control register c 51 ? 48 0xffff_e02c imcb interrupt mode control register b 47 ? 44 0xffff_e028 imca interrupt mode control register a 43 ? 40 0xffff_e024 imc9 interrupt mode control register 9 39 ? 36 0xffff_e020 imc8 interrupt mode control register 8 35 ? 32 0xffff_e01c imc7 interrupt mode control register 7 31 ? 28 0xffff_e018 imc6 interrupt mode control register 6 27 ? 24 0xffff_e014 imc5 interrupt mode control register 5 23 ? 20 0xffff_e010 imc4 interrupt mode control register 4 19 ? 16 0xffff_e00c imc3 interrupt mode control register 3 15 ? 12 0xffff_e008 imc2 interrupt mode control register 2 11 ? 8 0xffff_e004 imc1 interrupt mode control register 1 7 ? 4 0xffff_e000 imc0 interrupt mode control register 0 3 ? 0 interrupt vector register ( ivr ): indicates the vector for the so urce of each interrupt generated . 7 6 5 4 3 2 1 0 ivr bit symbol ivr7 ivr6 ivr5 ivr4 (0xffff_e040) read/write r after reset 0 0 0 0 0 0 0 0 function indicates the vectors for generated interrupt sources. 15 14 13 12 11 10 9 8 bit symbol i v r 9 i v r 8 read/write r/w r after reset 0 0 0 0 0 0 0 0 function indicates the vectors for generated interrupt sources. 23 22 21 20 19 18 17 16 bit symbol read/write r/w after reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r/w after reset 0 0 0 0 0 0 0 0 function tmp1942cy/cz tmp1942cy/cz-46 interrupt mode control registers : set the priority level and active state for each interrupt source and set whether the interrupt is to be used to activate the dmac . 7 6 5 4 3 2 1 0 imc0 bit symbol eim01 eim00 dm0 il02 il01 il00 (0xffff_e000) read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level other settings are not allowed. sets whether or not to activate the dmac. 0: not set. 1: set interrup t number 0 to activate the dmac. sets the priority level for interrupt number 0 (software set) when dm0 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm0 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim11 eim10 dm1 il12 il11 il10 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrup t number 1 to activate the dmac. sets the priority level for interrupt number 1 (int0) when dm1 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim21 eim20 dm2 il22 il21 il20 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrup t number 2 to activate the dmac. sets the priority level for interrupt number 2 (int1) when dm2 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim31 eim30 dm3 il32 il31 il30 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrup t number 3 to activate the dmac. sets the priority level for interrupt number 3 (int2) when dm3 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-47 7 6 5 4 3 2 1 0 imc1 bit symbol eim41 eim40 dm4 il42 il41 il40 (0xffff_e004) read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 4 t o activate the dmac. sets the priority level for interrupt number 4 (int3) when dm4 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm4 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim51 eim50 dm5 il52 il51 il50 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 5 t o activate the dmac. sets the priority level for interrupt number 5 (int4) when dm5 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm5 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim61 eim60 dm6 il62 il61 il60 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 6 t o activate the dmac. sets the priority level for interrupt number 6 (kwup) when dm6 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm6 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim71 eim70 dm7 il72 il71 il70 read/write r/w after reset 0 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 7 t o activate the dmac. sets the priority level for interrupt number 7 (intb/c/d/e) when dm7 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm7 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-48 7 6 5 4 3 2 1 0 imc2 bit symbol eim81 eim80 dm8 il82 il81 il80 (0xffff_e008) read/write r/w after reset 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 15 14 13 12 11 10 9 8 bit symbol eim91 eim90 dm9 il92 il91 il90 read/write r/w after reset 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 23 22 21 20 19 18 17 16 bit symbol eima1 eima0 dma ila2 ila1 ila0 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 10 to activate the dmac. sets the priority level for interrupt number 10 (int5) when dma = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dma = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eimb1 eimb0 dmb ilb2 ilb1 ilb0 read/write r/w after reset 0 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 11 to activate the dmac. sets the priority level for interrupt number 11 (int6) when dmb = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dmb = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-49 7 6 5 4 3 2 1 0 imc3 bit symbol eimc1 eimc0 dmc ilc2 ilc1 ilc0 (0xffff_e00c) read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 12 to activate the dmac. sets the priority level for interrupt number 12 (int7) when dmc = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dmc = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eimd1 eimd0 dmd ild2 ild1 ild0 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 13 to activate the dmac. sets the priority level for interrupt number 13 (int8) when dmd = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dmd = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eime1 eime0 dme ile2 ile1 ile0 read/write r/w after reset 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 14 to activate the dmac. sets the priority level for interrupt number 14 (int9) when dme = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dme = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eimf1 eimf0 dmf ilf2 ilf1 ilf0 read/write r/w after reset 0 0 0 0 0 0 0 function sets the active state of the interrupt request. 00: low level 01: high level 10: falling edge 11: rising edge sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 15 to activate the dmac. sets the priority level for interrupt number 15 (inta) when dmf = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dmf = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-50 7 6 5 4 3 2 1 0 imc4 bit symbol eim101 eim100 dm10 il102 il101 il100 (0xffff_e010) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 16 to activate the dmac. sets the priority level for interrupt number 16 (intrx0) when dm10 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm10 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim111 eim110 dm11 il112 il111 il110 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 17 to activate the dmac. sets the priority level for interrupt number 16 (inttx0) when dm11 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm11 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim121 eim120 dm12 il122 il121 il120 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 18 to activate the dmac. sets the priority level for interrupt number 18 (intrx1) when dm12 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm12 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim131 eim130 dm13 il132 il131 il130 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 19 to activate the dmac. sets the priority level for interrupt number 19 (inttx1) when dm13 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm13 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-51 7 6 5 4 3 2 1 0 imc5 bit symbol eim141 eim140 dm14 il142 il141 il140 (0xffff_e014) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 20 to activate the dmac. sets the priority level for interrupt number 20 (ints2) when dm14 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm14 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim151 eim150 dm15 il152 il151 il150 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 21 to activate the dmac. sets the priority level for interrupt number 21 (intrx3) when dm15 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm15 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim161 eim160 dm16 il162 il161 il160 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 22 to activate the dmac. sets the priority level for interrupt number 22 (inttx3) when dm16 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm16 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim171 eim170 dm17 il172 il171 il170 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 23 to activate the dmac. sets the priority level for interrupt number 23 (intadhp) when dm17 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm17 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-52 7 6 5 4 3 2 1 0 imc6 bit symbol eim181 eim180 dm18 il182 il181 il180 (0xffff_e018) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 24 to activate the dmac. sets the priority level for interrupt number 24 (intadm) when dm18 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm18 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim191 eim190 dm19 il192 il191 il190 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 25 to activate the dmac. sets the priority level for interrupt number 25 (intta0) when dm19 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm19 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim1a1 eim1a0 dm1a il1a2 il1a1 il1a0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 26 to activate the dmac. sets the priority level for interrupt number 26 (intta1) when dm1a = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1a = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim1b1 eim1b0 dm1b il1b2 il1b1 il1b0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 27 to activate the dmac. sets the priority level for interrupt number 27 (intta2) when dm1b = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1b = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-53 7 6 5 4 3 2 1 0 imc7 bit symbol eim1c1 eim1c0 dm1c il1c2 il1c1 il1c0 (0xffff_e01c) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 28 to activate the dmac. sets the priority level for interrupt number 28 (intta3) when dm1c = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1c = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim1d1 eim1d0 dm1d il1d2 il1d1 il1d0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 29 to activate the dmac. sets the priority level for interrupt number 29 (inttb0) when dm1d = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1d = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim1e1 eim1e0 dm1e il1e2 il1e1 il1e0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 30 to activate the dmac. sets the priority level for interrupt number 30 (inttb1) when dm1e = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1e = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim1f1 eim1f0 dm1f il1f2 il1f1 il1f0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 31 to activate the dmac. sets the priority level for interrupt number 31 (intrx4) when dm1f = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm1f = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-54 7 6 5 4 3 2 1 0 imc8 bit symbol eim201 eim200 dm20 il202 il201 il200 (0xffff_e020) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 32 to activate the dmac. sets the priority level for interrupt number 32 (inttx4) when dm20 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm20 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim211 eim210 dm21 il212 il211 il210 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 33 to activate the dmac. sets the priority level for interrupt number 33 (intrx5) when dm21 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm21 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim221 eim220 dm22 il222 il221 il220 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 34 to activate the dmac. sets the priority level for interrupt number 34 (inttx5) when dm22 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm22 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim231 eim230 dm23 il232 il231 il230 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-55 7 6 5 4 3 2 1 0 imc9 bit symbol eim241 eim240 dm24 il242 il241 il240 (0xffff_e024) read/write r/w after reset 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 15 14 13 12 11 10 9 8 bit symbol eim251 eim250 dm25 il252 il251 il250 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 37 to activate the dmac. sets the priority level for interrupt number 37 (intta4) when dm25 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm25 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim261 eim260 dm26 il262 il261 il260 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 38 to activate the dmac. sets the priority level for interrupt number 38 (intta5) when dm26 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm26 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim271 eim270 dm27 il272 il271 il270 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 39 to activate the dmac. sets the priority level for interrupt number 39 (intta6) when dm27 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm27 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-56 7 6 5 4 3 2 1 0 imca bit symbol eim281 eim280 dm28 il282 il281 il280 (0xffff_e028) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 40 to activate the dmac. sets the priority level for interrupt number 40 (intta7) when dm28 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm28 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim291 eim290 dm29 il292 il291 il290 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 41 to activate the dmac. sets the priority level for interrupt number 41 (intta8) when dm29 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm29 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim2a1 eim2a0 dm2a il2a2 il2a1 il2a0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 42 to activate the dmac. sets the priority level for interrupt number 42 (intta9) when dm2a = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2a = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim2b1 eim2b0 dm2b il2b2 il2b1 il2b0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 43 to activate the dmac. sets the priority level for interrupt number 43 (inttaa) when dm2b = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2b = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-57 7 6 5 4 3 2 1 0 imcb bit symbol eim2c1 eim2c0 dm2c il2c2 il2c1 il2c0 (0xffff_e02c) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 44 to activate the dmac. sets the priority level for interrupt number 44 (inttab) when dm2c = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2c = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim2d1 eim2d0 dm2d il2d2 il2d1 il2d0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 45 to activate the dmac. sets the priority level for interrupt number 45 (inttba) when dm2d = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2d = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim2e1 eim2e0 dm2e il2e2 il2e1 il2e0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 46 to activate the dmac. sets the priority level for interrupt number 46 (inttbb) when dm2e = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2e = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim2f1 eim2f0 dm2f il2f2 il2f1 il2f0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 47 to activate the dmac. sets the priority level for interrupt number 47 (inttbc) when dm2f = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm2f = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-58 7 6 5 4 3 2 1 0 imcc bit symbol eim301 eim300 dm30 il302 il301 il300 (0xffff_e030) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 48 to activate the dmac. sets the priority level for interrupt number 48 (inttbd) when dm30 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm30 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim311 eim310 dm31 il312 il311 il310 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 49 to activate the dmac. sets the priority level for interrupt number 49 (inttb2) when dm31 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm31 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim321 eim320 dm32 il322 il321 il320 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 50 to activate the dmac. sets the priority level for interrupt number 50 (inttb3) when dm32 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm32 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim331 eim330 dm33 il332 il331 il330 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 51 to activate the dmac. sets the priority level for interrupt number 51 (inttb4) when dm33 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm33 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-59 7 6 5 4 3 2 1 0 imcd bit symbol eim341 eim340 dm34 il342 il341 il340 (0xffff_e034) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 52 to activate the dmac. sets the priority level for interrupt number 52 (inttb5) when dm34 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm34 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim351 eim350 dm35 il352 il351 il350 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 53 to activate the dmac. sets the priority level for interrupt number 53 (inttb6) when dm35 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm35 = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim361 eim360 dm36 il362 il361 il360 read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 54 to activate the dmac. sets the priority level for interrupt number 54 (inttb7) when dm36 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm36 = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim371 eim370 dm37 il372 il371 il370 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 55 to activate the dmac. sets the priority level for interrupt number 55 (inttb8) when dm37 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm37 = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-60 7 6 5 4 3 2 1 0 imce bit symbol eim381 eim380 dm38 il382 il381 il380 (0xffff_e038) read/write r/w after reset 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 56 to activate the dmac. sets the priority level for interrupt number 56 (inttb9) when dm38 = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm38 = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim391 eim390 dm39 il392 il391 il390 read/write r/w after reset 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 23 22 21 20 19 18 17 16 bit symbol eim3a1 eim3a0 dm3a il3a2 il3a1 il3a0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 01. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 58 to activate the dmac. sets the priority level for interrupt number 58 (intrtc) when dm3a = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3a = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim3b1 eim3b0 dm3b il3b2 il3b1 il3b0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 11. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 59 to activate the dmac. sets the priority level for interrupt number 59 (intad) when dm3b = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3b = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-61 7 6 5 4 3 2 1 0 imcf bit symbol eim3c1 eim3c0 dm3c il3c2 il3c1 il3c0 (0xffff_e03c) read/write r/w after reset 0 0 0 0 0 0 function must be set to 10. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 60 to activate the dmac. sets the priority level for interrupt number 60 (intdma0) when dm3c = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3c = 1. 000-011: 0 to 3 100-111: invalid settings 15 14 13 12 11 10 9 8 bit symbol eim3d1 eim3d0 dm3d il3d2 il3d1 il3d0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 10. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 61 to activate the dmac. sets the priority level for interrupt number 61 (intdma1) when dm3d = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3d = 1. 000-011: 0 to 3 100-111: invalid settings 23 22 21 20 19 18 17 16 bit symbol eim3e1 eim3e0 dm3e il3e2 il3e1 il3e0 read/write r/w after reset 0 0 0 0 0 0 function must be set to 10. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 62 to activate the dmac. sets the priority level for interrupt number 62 (intdma1) when dm3e = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3e = 1. 000-011: 0 to 3 100-111: invalid settings 31 30 29 28 27 26 25 24 bit symbol eim3f1 eim3f0 dm3f il3f2 il3f1 il3f0 read/write r/w after reset 0 0 0 0 0 0 0 function must be set to 10. sets whether or not to activate the dmac. 0: not set. 1: set interrupt number 63 to activate the dmac. sets the priority level for interrupt number 63 (intdma2) when dm3f = 0. 000: disable interrupt. 001-111: 1 to 7 selects a dmac channel when dm3f = 1. 000-011: 0 to 3 100-111: invalid settings note : before enabling the above interrupt requ ests, be sure to set their active state. tmp1942cy/cz tmp1942cy/cz-62 interrupt request clear register : sets the value of ivr < livr9 : livr4 > for the interrupt whose request is to be cleared . 7 6 5 4 3 2 1 0 intclr bit symbol ? ? eiclr5 eiclr4 eiclr3 eiclr2 eiclr1 eiclr0 (0xffff_e060) read/write ? ? w after reset ? ? ? ? ? ? ? ? function sets the value of ivr<9:4> for the interrupt whose request is to be cleared. note1: do not clear an interrupt request before reading the corresponding ivr value. note2: follow the steps below to disable a particular interrupt with the interrupt controller (intc). 1. globally disable the acceptance of interrupts by the core processo r by clearing the iec bit of the status register. 2. disable the desired interrupt with the intc by clearing the ilx[2:0] field of the imcxx register. 3. execute the sync instruction. 4. enable the acceptance of interrupts by the core processor by setting the iec bit of the status register. example: mtc0 r0, r31 ; _di () ; sb r0, imc** ; imc** = 0 ; sync ; _sync () ; mtc0 $sp, r31 ; _ei () ; tmp1942cy/cz tmp1942cy/cz-63 3.5 i/o ports the tmp1942 has 108 i / o port pins . all the port pins except a few share pins with alternate functions . they can be individually programmed as general - purpose i / o or dedicated i / o for the on - chip cpu or peripherals . table 3.5.1 programmable i/o ports(1/2) port pin name # of pins direction pull resistor direction programmability alternate functions port 0 p00~p07 8 input/output bitwise ad0~ad7 port 1 p10~p17 8 input/output bitwise ad8~ad15 a8~a15 port 2 p20~p27 8 input/output bitwise a0~a7 a16~a23 p30 1 output bitwise p31 1 output bitwise p32 1 input/output pull up bitwise p33 1 input/output pull up bitwise p34 1 input/output pull up bitwise p35 1 input/output pull up bitwise p36 1 input/output pull up bitwise port 3 p37 1 input/output pull up bitwise p40 1 input/output pull up bitwise p41 1 input/output pull up bitwise p42 1 input/output pull up bitwise p43 1 input/output pull up bitwise port 4 p44 1 input/output bitwise scout port 5 p50~p57 8 input fixed an0~an7 adtrg port 6 p60~p67 8 input fixed an8~an15 key0-key7 p90 1 input/output bitwise key8 p91 1 input/output bitwise key9 p92 1 input/output bitwise tb40ut p93 1 input/output bitwise tb5out p94 1 input/output bitwise tb6out p95 1 input/output bitwise tb7in0 p96 1 input/output bitwise tb7in1 port 9 p97 1 input/output bitwise tb7out cs3 cs2 cs1 dsu r/w busak busrq wait hwr wr rd cs0 tmp1942cy/cz tmp1942cy/cz-64 table 3.5.1 programmable i/o ports(2/2) port pin name # of pins direction pull resistor direction programmability alternate functions pa0 1 input/output bitwise tb0in0 int3 pa1 1 input/output bitwise tb0in1 int4 pa2 1 input/output bitwise tb0out pa3 1 input/output bitwise tb1in0 int5 pa4 1 input/output bitwise tb1in1 int6 pa5 1 input/output bitwise tb1out pa6 1 input/output bitwise ta1out port a pa7 1 input/output bitwise ta0in keya pb0 1 input/output bitwise tb2in0 intb pb1 1 input/output bitwise tb2in1 intc pb2 1 input/output bitwise tb2out tb4in0 pb3 1 input/output bit tb3in0 intd pb4 1 input/output bit tb3in1 inte pb5 1 input/output bit tb3out tb4in1 pb6 1 input/output bit ta3out port b pb7 1 input/output bit ta2in int7 keyb pc0 1 input/output bit ta4in int8 pc1 1 input/output bit ta6in int9 pc2 1 input/output bit ta8in inta pc3 1 input/output bit ta5out pc4 1 input/output bit taain pc5 1 input/output bit ta7out pc6 1 input/output bit tb8in0 keyc port c pc7 1 input/output bit tb8in1 ta9out pd0 1 input/output bit txd0 tb9in0 pd1 1 input/output bit rxd0 tb9in1 pd2 1 input/output bit sclk0 pd3 1 input/output bit txd1 tbain0 pd4 1 input/output bit rxd1 tbain1 pd5 1 input/output bit sclk1 tabout pd6 1 input/output bit xt1 port d pd7 1 input/output bit xt2 pe0 1 input/output bit txd3 pe1 1 input/output bit rxd3 pe2 1 input/output bit sclk3 pe3 1 input/output bit txd4 pe4 1 input/output bit rxd4 pe5 1 input/output bit sclk4 pe6 1 input/output bit int1 boot port e pe7 1 input/output bit int2 intlv pf0 1 input/output bit txd5 pf1 1 input/output bit rxd5 keyd pf2 1 input/output bit sclk5 pf3 1 input/output bit sck pf4 1 input/output bit so sda pf5 1 input/output bit si scl port f pf6 1 input/output bit int0 cts0 cts1 cts3 cts4 cts5 tmp1942cy/cz tmp1942cy/cz-65 table 3.5.2 i/o port programmability (1/4) i/o register settings port pin name direction / function pn pncr pnfc pnfc2 input - 0 output - 1 port 0 p00~p07 ad0~ad7 bus - - input - 0 0 output - 1 0 ad8~ad15 bus - 0 1 port 1 p10~p17 a8~a15 bus - 1 1 input - 0 0 output - 1 0 a0~a7 bus - 0 1 port 2 p20~p27 a16~a23 bus - 1 1 output - 0 p30 - 1 output - 0 p31 - 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p32 - 1 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p33 - 0 0 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p34 - 0 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p35 - 1 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p36 - 1 1 input 1 0 port 3 p37 output 1 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p40 - - 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 port 4 p41 - - 1 hwr busrq busak r/w wr wait rd cs0 cs 1 tmp1942cy/cz tmp1942cy/cz-66 table 3.5.2 i/o port programmability (2/4) i/o register settings port pin name direction / function pn pncr pnfc pnfc2 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p42 - - 1 input(rstup=1) 1 0 0 input(rstup=0) 0 0 0 output - 1 0 p43 - - 1 input 1 0 0 output 1 1 0 port 4 p44 scout - - 1 input - 0 an0~an7 - 0 port 5 p50~p57 adtrg - 1 input - 0 an8~an15 - 0 port 6 p60~p67 key0~7 - 1 input - 0 0 p90~p97 output - 1 0 p90 key8 - 0 1 p91 key9 - 0 1 p92 tb40ut - 1 1 p93 tb5out - 1 1 p94 tb6out - 1 1 p95 tb7in0 - 0 1 p96 tb7in1 - 0 1 port 9 p97 tb7out - 1 1 input - 0 0 pa0~pa7 output - 1 0 tb0in0 - 0 1 pa0 int3 - 0 1* tb0in1 - 0 1 pa1 int4 - 0 1* pa2 tb0out - 1 1 tb1in0 - 0 1 pa3 int5 - 0 - tb1in1 - 0 1 pa4 int6 - 0 - pa5 tb1out - 1 1 pa6 ta1out - 1 1 ta0in - 0 1 port a pa7 keya - 0 1 cs 2 cs 3 tmp1942cy/cz tmp1942cy/cz-67 table 3.5.2 i/o port programmability (3/4) i/o register settings port pin name direction / function pn pncr pnfc pnfc2 input - 0 0 pb0~pb7 output - 1 0 tb2in0 - 0 1 pb0 intb - 0 1* tb2in1 - 0 1 pb1 intc - 0 1* tb2out - 1 1 pb2 tb4in0 - 0 1 tb3in0 - 0 1 pb3 intd - 0 1* tb3in1 - 0 1 pb4 inte - 0 1* tb3out - 1 1 pb5 tb4in1 - 0 1 pb6 ta3out - 1 1 ta2in - 0 1 int7 - 0 - port b pb7 keyb - 0 1 input - 0 0 pc0~pc7 output - 1 0 ta4in - 0 1 pc0 int8 - 0 - ta6in - 0 1 pc1 int9 - 0 - ta8in - 0 1 pc2 inta - 0 - pc3 ta5out - 1 1 pc4 taain - 0 1 pc5 ta7out - 1 1 tb8in0 - 0 1 pc6 keyc - 0 1 tb8in1 - 0 1 port c pc7 ta9out - 1 1 input - 0 0 - pd0~pd7 output - 1 0 - txd0 - 1 1 - pd0 tb9in0 - 0 1 - rxd0 - 0 1 - pd1 tb9in1 - 0 1 - sclk0(input) - 0 1 - sclk0(output) - 1 1 - pd2 cts0 - 0 1 - txd1 - 1 1 - pd3 tbain0 - 0 1 - rxd1 - 0 1 - port d pd4 tbain1 - 0 1 - tmp1942cy/cz tmp1942cy/cz-68 table 3.5.2 i/o port programmability (4/4) i/o register settings port pin name direction / function pn pncr pnfc pnfc2 sclk1(input) - 0 1 0 sclk1(output) - 1 1 0 cts3 - 0 1 0 pd5 tabout - 1 0 1 pd6 xt1 - - - - port d pd7 xt2 - - - - input - 0 0 pe0~pe7 output - 1 0 pe0 txd3 - 1 1 pe1 rxd3 - 0 1 sclk3(input) - 0 1 sclk3(output) - 1 1 pe2 cts3 - 0 1 pe3 txd4 - 1 1 pe4 rxd4 - 0 1 sclk4(input) - 0 1 sclk4(output) - 1 1 pe5 cts4 - 0 1 pe6 int1 - 0 1* port e pe7 int2 - 0 1* input - 0 0 pf0~pf6 output - 1 0 pf0 txd5 - 1 1 rxd5 - 0 1 pf1 keyd - 0 1 sclk5(input) - 0 1 sclk5(output) - 1 1 pf2 cts - 0 1 sck(input) - 0 1 pf3 sck(output) - 1 1 so - 1 1 pf4 sda - 1 1 si - 1 1 pf5 scl - 1 1 port f pf6 int0 - 0 1* x: don?t care pn: port n register, pncr: port n control register, pnfc: port n function register *: set this bit when using the pin for a stop mode termi nation interrupt with syscr tmp1942cy/cz tmp1942cy/cz-69 3.5.1 port 0 (p00-p07) port 0 is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . use the control register p0cr to set the port for input or output . a reset clears all bits of p0cr to 0 and puts port 0 in input mode . in add itio n to functioning as a general - purpose input / output port , this port can also function as an address/ data bus ( ad0 - ad7 ). when external memory is accessed , this port automatically functions as an address/ data bus ( ad0 - ad7 ), with all bits of p0cr cleared to 0 . figure 0.1 port 0 (p00-p07) note: the above system diagram does not represent the address/data bus function. direction control (bitwise) output latch read p0 port 0 p00-p07 (ad0-ad7) output buffer write to p0 write to p0cr reset internal data bus stop drive tmp1942cy/cz tmp1942cy/cz-70 port 0 register 7 6 5 4 3 2 1 0 p0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 (0xffff_f000) read/write r/w after reset input mode (output latch register cleared to 0) port 0 control register 7 6 5 4 3 2 1 0 p0cr bit symbol p07c p06c p05c p04c p03c p02c p01c p00c (0xffff_f002) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out (functions as ad7-ad0 when external area is accessed, with the register cleared to 0.) input/output setting for port 0 0 input 1 output figure 0.2 registers related to port 0 tmp1942cy/cz tmp1942cy/cz-71 3.5.2 port 1 (p10-p17) port 1 is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register p1cr and function register p1fc are used to set the port for input or output . a reset clears all bits of output latch p1 and all b its of p1cr and p1fc to 0 , putting port 1 in input mode . in addition to functioning as a general - purpose input / output port , this port can also function as an address/ data bus ( ad8 - ad15 ) or an address bus ( a8 - a15 ). to access external memory , set this port to an addres s bu s or address / data bus using p1cr and p1fc . figure 0.3 port 1 (p10-p17) note: the above system diagram does not represent the address/data bus function. function control (bitwise) direction control (bitwise) output latch read p1 port 1 p10-p17 (ad8-ad15/a8-a15) output buffer write to p1fc write to p1 write to p1cr reset internal data bus stop drive tmp1942cy/cz tmp1942cy/cz-72 port 1 register 7 6 5 4 3 2 1 0 p1 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 (0xffff_f001) read/write r/w after reset input mode (output latch register cleared to 0) port 1 control register 7 6 5 4 3 2 1 0 p1cr bit symbol p17c p16c p15c p14c p13c p12c p11c p10c (0xffff_f004) read/write w after reset 0 0 0 0 0 0 0 0 function << refer to p1fc. >> port 1 function register 7 6 5 4 3 2 1 0 p1fc bit symbol p17f p16f p15f p14f p13f p12f p11f p10f (0xffff_f005) read/write w after reset 0 0 0 0 0 0 0 0 function p1fc/p1cr = 00: in, 01: out, 10: ad15-8, 11: a15-8 function settings for port 1 p1fc tmp1942cy/cz tmp1942cy/cz-73 3.5.3 port 2 (p20-p27) port 2 is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register p2cr and function register p2fc are used to set the port for input or output . a reset sets all bits of output latch p2 to 1 and clears all b its of p2cr and p2fc to 0 , putting port 2 in input mode . in addition to functioning as a general - purpose input / output port , this port can function as an address bus ( a0 - a7 or a16 - a23 ). figure 0.5 port 2 (p20-p27) direction control (bitwise) read p2 port 2 p20-p27 (a0-a7/a16-a23) output buffer write to p2 write to p2fc write to p2cr s y b a a0-7 a16-23 reset internal data bus selector selector s y b a output latch function control (bitwise) stop drive tmp1942cy/cz tmp1942cy/cz-74 port 2 control register 7 6 5 4 3 2 1 0 p2 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 (0xffff_f012) read/write r/w after reset input mode (output latch register set to 1) port 2 control register 7 6 5 4 3 2 1 0 p2cr bit symbol p27c p26c p25c p24c p23c p22c p21c p20c (0xffff_f014) read/write w after reset 0 0 0 0 0 0 0 0 function << refer to p2fc.>> port 2 function register 7 6 5 4 3 2 1 0 p2fc bit symbol p27f p26f p25f p24f p23f p22f p21f p20f (0xffff_f015) read/write w after reset 0 0 0 0 0 0 0 0 function p2fc/p2cr = 00: in, 01: out, 10: a7-0, 11: a23-16 function settings for port 2 p2cr p2fc tmp1942cy/cz tmp1942cy/cz-75 3.5.4 port 3 (p30-p37) port 3 is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output , with the exception that p30 and p31 are output - only . the control register p3cr and function register p3fc are used to set the port for input or output . a reset sets b its p3 0 , p31 and p37 of the output latch to 1 . bits p32 to p36 are set to 1 by a reset if rstpup is high or cleared to 0 if rstpup is low. all bits of p3cr ( bits 0 and 1 not used ) and p3fc ( bits 3 and 7 not used ) are cleared to 0 by a reset , with p30 and p3 1 ou tputting a high signal and p32 to p36 placed in input mode with pull - up resistors enabled ( if rstpup is high ) or disabled ( if rstpup is low ). p37 is placed in input mode with a pull - up resistor enable d re gardless of the value of rstpup . in addition to functioning as a general - purpose input / output port , this port can also input and output the cpu's control and status signals . the rd strobe is output only when an external address area is being accessed while the p30 pi n is set for rd output (< p30f > = 1 ). similarly , the wr strobe is output only when an external address area is being accessed while the p31 pin is set for wr output (< p31f > = 1 ). p32 and p36 have their pull - up resistors enabled when busak = 0 while < p3xfc > = 1 . figure 0.7 port 3 (p30, p31) rd , wr read p3 output buffer function control (bitwise) p30 ( rd ) p31 ( wr ) write to p3 write to p3fc reset internal data bus selector s output latch b a s tmp1942cy/cz tmp1942cy/cz-76 figure 0.8 port 3 (p32, p35, p36) read p3 output buffer function control (bitwise) direction control (bitwise) p32 ( hwr ) p35 ( busak ) p36 ( w/ r) p-ch write to p3 write to p3fc write to p3cr reset internaldatabus selector s a b stop drive s r output latch rstpup hwr , busak , w/ r reset programmable pull-up resistor tmp1942cy/cz tmp1942cy/cz-77 figure 0.9 port 3 (p33, p34) read p3 output buffer direction control (bitwise) p33 ( wait ) p-ch write to p3 write to p3cr reset stop drive s r output latch rstpup reset programmable pull-up resistor internal wait internal data bus read p3 output buffer direction control (bitwise) p34 ( busrq ) p-ch write to p3 write to p3cr reset internal data bus stop drive s r output latch rstpup reset programmable pull-up resistor internal busrq function control (bitwise) write to p3fc tmp1942cy/cz tmp1942cy/cz-78 figure 0.10 port 3 (p37) read p3 output buffer direction control (bitwise) p37 ( dsu ) p-ch write to p3 write to p3cr reset stop drive programmable pull-up resistor internal dsu internal data bus s output latch tmp1942cy/cz tmp1942cy/cz-79 port 3 register 7 6 5 4 3 2 1 0 p3 bit symbol p37 p36 p35 p34 p33 p32 p31 p30 (0xffff_f018) read/write r/w after reset input mode output mode rstpup = 1 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 1 rstpup = 0 1 (pull-up) 0 0 0 0 0 1 1 port 3 control register 7 6 5 4 3 2 1 0 p3cr bit symbol p37c p36c p35c p34c p33c p32c ? ? (0xffff_f01a) read/write w ? ? after reset 0 0 0 0 0 0 ? ? function 0: in 1: out input/output settings for port 3 0 input 1 output port 3 function register 7 6 5 4 3 2 1 0 p3fc bit symbol ? p36f p35f p34f ? p32f p31f p30f (0xffff_f01b) read/write w after reset ? 0 0 0 ? 0 0 0 function 0: port 1: w/r 0: port 1: busak 0: port 1: busrq 0: port 1: hwr 0: port 1: wr 0: port 1: rd busrq settings p30 ( rd ) function settings p3fc tmp1942cy/cz tmp1942cy/cz-80 3.5.5 port 4 (p40-p44) port 4 is a 5 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register p4cr and function register p4fc are used to set the port for input or output . bits p41 to p44 of the output latch register are set to 1 by a reset if rstpup is hi gh or cleared to 0 if rstpup is low . bit p44 of the output latch register is set to 1 regardless of the value of rstpup . all bits of p4cr and p4fc are cleared to 0 by a reset , with p40 to p43 pla ced in i nput mode with pull - up resistors enabled ( if rstpup is high) or disabled ( if rstpup is low ). p44 is placed in input mode with a pull - up resistor disabled regardless of the value of rstpup . in addition to functioning as a general - purpose input / output port , p40 - p4 3 can also outp ut the chip select signals ( cs0 - cs3 ), and p44 functions as the scout pin , outputting the system clock . figure 0.12 port 4 (p40-p43) read p4 output latch function control (bitwise) direction control (bitwise) p40 ( cs0 ) p41 ( cs1 ) p42 ( cs2 ) p43 ( cs3 ) p-ch write to p4 write to p4fc write to p4cr reset internal data bus selector s a b stop drive s r output latch rstpup cs0 , cs1 , cs2 , cs3 reset programmable pull-up resistor tmp1942cy/cz tmp1942cy/cz-81 figure 0.13 port 4 (p44) selector r function control (bitwise) r direction control (bitwise) internal data bus reset write to p4cr read p4 fs clock f sys clock p44 (scout) y s b a write to p4fc syscr3 tmp1942cy/cz tmp1942cy/cz-82 port 4 register 7 6 5 4 3 2 1 0 p4 bit symbol ? ? ? p44 p43 p42 p41 p40 (0xffff_f01e) read/write ? ? ? r/w after reset ? ? ? input mode rstpup=1 1 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) rstpup=0 1 0 0 0 0 rstpup = 1 rstpup = 0 port 4 control register 7 6 5 4 3 2 1 0 p4cr bit symbol ? ? ? p44c p43c p42c p41c p40c (0xffff_f020) read/write ? ? ? w after reset ? ? ? 0 0 0 0 0 0: in 1: out port 4 function register 7 6 5 4 3 2 1 0 p4fc bit symbol ? ? ? p44f p43f p42f p41f p40f (0xffff_f021) read/write ? ? ? w after reset ? ? ? 0 0 0 0 0 function 0: port 0: port 1: scout 1: cs 0 port (p40) 1 cs0 0 port (p41) 1 cs1 0 port (p42) 1 cs2 0 port (p43) 1 cs3 figure 0.14 registers related to port 4 tmp1942cy/cz tmp1942cy/cz-83 3.5.6 port 5 (p50-p57) port 5 is an 8 - bit input - only port , and is shared with the a / d converter's analog input pins . p57 also functions as the a / d converter's a / d trigger input pin . figure 0.15 port 5 (p50-p57) read a/d read port 5 port 5 p50-p56 (an0-an7) internal data bus channel selector a/d converter conversion result register read a/d read port 5 port 5 p57 (an7)/ adtrg internal data bus channel selector a/d converter conversion result register function control adtrg (p57 only) write p5fc tmp1942cy/cz tmp1942cy/cz-84 port 5 register 7 6 5 4 3 2 1 0 p5 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 (0xffff_f040) read/write r after reset input mode port 5 function register 7 6 5 4 3 2 1 0 p5fc bit symbol p57f ? ? ? ? ? ? ? (0xffff_f043) read/write w ? after reset 0 ? ? ? ? ? ? ? function 0: port or a/d input 1: adtrg figure 0.16 port 5 (p50-p57) note 1: use a/d converter mode register admod4 to select a/d converter input channels and to enable a/d trigger input for p57. note 2: to use adtrg , first set tmp1942cy/cz tmp1942cy/cz-85 3.5.7 port 6 (p60-p67) port 6 is an 8 - bit input - only port , and is shared with the a / d converter's analog input pins and key input pins . a reset clears p6fc to 0 , placing port 6 in a / d or port input mode . writing a 1 to a bit of p6fc enables the corresponding pi n to be us ed as a key input pin . port 6 has pull - up resistors , which are enabled only for those pins for which kwupcnt < pe > is set to 1 in the key on wake - up circuit and key input is enabled in kwupstn . for details , refer to the description of th e key on wake - up function . figure 0.17 port 6 (p60-p67) port 6 register 7 6 5 4 3 2 1 0 p6 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 (0xffff_f041) read/write r after reset input mode port 6 function register 7 6 5 4 3 2 1 0 p6fc bit symbol p67f p66f p65f p64f p63f p62f p61f p60f (0xffff_f045) read/write w after reset 0 function 0: port or a/d input 1: key input figure 0.18 registers related to port 6 read a/d read port 6 port 6 p60-67 (an8-15)/ key0-7 internal data bus channel selector a/d converter conversion result register function control key0-7 write p6fc keymen pe selector y a b tg dpe fs tmp1942cy/cz tmp1942cy/cz-86 3.5.8 port 9 (p90-p97) port 9 is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register p9cr is used to set the port for input or output . a reset clears p9cr to 0 , putting port 9 in input mode . in addition to f unctioning as an in put / output port , the pins of this port can also function as various input / output pins : p90 and p91 function as key input , p92 to p94 and p97 as 16 - bit timer output , and p95 and p96 as 16- bit timer input . these functions are enabled by setting th e corres ponding bits of p9fc to 1 . a reset clears p9cr and p9fc to 0 , placing port 9 in input mode . pins p90 and p91 have pull - up resistors, which are enabled only for those pins for which kwupcnt < pe> is set to 1 in the key on wake - up circui t and key i nput is enabled in kwupstn . for details , refer to the description of the key on wake - up function . when a pin is functioning as a port pin , its pull - up resistor is disabled . when the dsu is enabled , port 9 functions as a dsu interface regardless of th e settin gs in p9cr and p9fc , so that the pins cannot be used as general - purpose port pins or peripheral function pins as described above . figure 0.19 port 9 (p90, p91) read p9 s output latch direction control (bitwise) write to p9 write to p9cr reset internal data bus stop drive function control write to p9fc output buffer keymen pe selector y a b tg dpe fs reset p90 (key8) p91 (key9) key8, 9 tmp1942cy/cz tmp1942cy/cz-87 figure 0.20 port 9 (p92-p97) p92 (tb4out) p93 (tb5out) p94 (tb6out) p97 (tb7out) reset write to p9fc read p9 write to p9 write to p9cr internal data bus function control (bitwise) direction control (bitwise) output latch a s selector b s stop drive timer f/f output tb4out: timer b4 tb5out: timer b5 tb6out: timer b6 tb7out: timer b7 s b selector a p95 (tb7in0) p96 (tb7in1) reset write to p9fc tb7in0, 1 read p9 write to p9 write to p9cr internal databus function control (bitwise) direction control (bitwise) output latch selector s s stop drive b a tmp1942cy/cz tmp1942cy/cz-88 port 9 register 7 6 5 4 3 2 1 0 p9 bit symbol p97 p96 p95 p94 p93 p92 p91 p90 (0xffff_f04c) read/write r/w after reset input mode (output latch register set to 1) port 9 control register 7 6 5 4 3 2 1 0 p9cr bit symbol p97c p96c p95c p94c p93c p92c p91c p90c (0xffff_f04e) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out input/output settings for port 9 0 input 1 output port 9 function register 7 6 5 4 3 2 1 0 p9fc bit symbol p97f p96f p95f p94f p93f p92f p91f p90f (0xffff_f04f) read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tb7out 0: port 1: tb7in1 0: port 1: tb7in0 0: port 1: tb6out 0: port 1: tb5out 0: port 1: tb4out 0: port 1: key9 0: port 1: key8 function corresponding p9fc bit corresponding p9cr bit port used select key8 input 1 0 p90 select key9 input 1 0 p91 select tb4out output 1 1 p92 select tb5out output 1 1 p93 select tb6out output 1 1 p94 select tb7in0 input 1 0 p95 select tb7in1 input 1 0 p96 select tb7out output 1 1 p97 figure 0.21 registers related to port 9 tmp1942cy/cz tmp1942cy/cz-89 3.5 3.5.9 port a (pa0-pa7) port a is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pacr is used to set the port for input or output . a reset clears pacr to 0 , putting port a in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pa0 , pa1 , pa3 and pa4 function as 16 - bit timer input or external interrupt input , pa2 and pa5 as 16 - bit timer output , pa6 as 8 - bit timer output , and pa7 as 8 - bit timer input or key input . these functions are enabled by setting the corresponding bits of pafc to 1 . a reset clears pacr and pafc to 0 , placing port a in input mode . pa7 has a pull - up resistor , which is enabled only when kwupcnt < pe > is set to 1 in the key on wake - up circuit and key input is enabled by setting 1 in pafc . when the pin is functioning as a port pin , its pull - up resistor is disabled . figure 3.5.21 port a (pa2, pa5, pa6) reset function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc tb0out tb1out ta1out write to pacr internal data bus s a selector b write to pa s b selector a timer f/f output read pa pa2 (tb0out) pa5 (tb1out) pa6 (ta1out) tmp1942cy/cz tmp1942cy/cz-90 figure 3.5.22 port a (pa0, pa1, pa7) function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc write to pacr reset internal data bus b selector a write to pa read pa pa0 (tb0in0/int3) pa1 (tb0in1/int4) s tb0in0, tb0in1 int3, int4 keya keymen pe selector y a b dpe tg fs function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc write to pacr reset internal data bus b selector a write to pa read pa pa7 (ta0in/keya) s ta0in reset tmp1942cy/cz tmp1942cy/cz-91 figure 3.5.23 port a (pa3, pa4) function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc write to pacr reset internal data bus b selector a write to pa read pa pa3 (tb1in0/int5) pa4 (tb1in1/int6) s tb1in0, tb1in1 int5, int6 tmp1942cy/cz port a register 7 6 5 4 3 2 1 0 pa bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (0xffff_f050) read/write r/w after reset input mode (output latch register set to 1) 1 1 1 1 1 1 1 1 port a control register 7 6 5 4 3 2 1 0 pacr bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c (0xffff_f052) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out input/output settings for port a 0 input 1 output port a function register 7 6 5 4 3 2 1 0 pafc bit symbol pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f (0xffff_f053) read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: ta0in keya 0: port 1: ta1out 0: port 1: tb1out 0: port 1: tb1in1 int6 0: port 1: tb1int0 int5 0: port 1: tb0out 0: port 1: tb0in1 int4 0: port 1: tb0in0 int3 function corresponding pafc bit corresponding pacr bit port used select tb0in0 input 1 0 select int3 input 1 (*1) 0 pa0 select tb0in1 input 1 0 select int4 input 1 (*1) 0 pa1 select tb0out output 1 1 pa2 select tb1in0 input 1 0 select int5 input need not be set 0 pa3 select tb1in1 input 1 0 select int6 input need not be set 0 pa4 select tb1out output 1 1 pa5 select ta1out output 1 1 pa6 select ta0in input 1 0 select keya input 1 0 pa7 (*1) set this bit when using the pin for a stop mode termination interrupt with syscr tmp1942cy/cz tmp1942cy/cz-93 3.5.10 port b (pb0-pb7) port b is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pbcr is used to set the port for input or output . a reset clears pbcr to 0 , putting port b in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pb0 , pb1 , pb3 and pb4 function as 16 - bit timer input or external interrupt input , pb2 and pb5 as 16 - bit timer input or output , pb7 as 8 - bit timer input , interrupt input or key input . these functions are enabled by setting the corresponding bits of pbfc to 1 . a reset clears pbcr and pbfc to 0 , placing port b in input mode . pb7 has a pull - up resistor , which is enabled only when kwupcnt < pe > is set to 1 in the key on wake - up circuit and key input is enabled in kwupstn . for details , refer to the description of the key on wake - up function . when the pin is functioning as a port pin , its pull - up resistor is disabled . figure 3.5.25 port b (pb2, pb5) function control (bitwise) direction control (bitwise) s output latch stop drive write to pbfc tb2out tb3out write to pbcr reset internal data bus s a selector b write to p7 s b selector a timer f/f output read to p7 pb2 (tb2out/tb4in0) pb5 (tb3out/tb4in1) tb4in0 tb4in1 tmp1942cy/cz tmp1942cy/cz-94 figure 3.5.26 port b (pb0, pb1, pb3, pb4, pb6) function control (bitwise) direction control (bitwise) s output latch stop drive write to pbfc write to pbcr reset internal data bus b selector a write to pb read pb pb0 (tb2in0/intb) pb1 (tb2in1/intc) pb3 (tb3in0/intd) pb4 (tb3in1/inte) s tb2in0, 1 tb3in0, 1 intb, c, d, e function control (bitwise) direction control (bitwise) s output latch stop drive write to pbfc (ta3out: timer a3) write to pbcr reset internal data bus s a selector b write to pb s b selector a timer f/f output read pb pb6 (ta3out) tmp1942cy/cz tmp1942cy/cz-95 figure 3.5.27 port b (pb7) int7 keyb keymen pe selector y a b dpe tg fs function control (bitwise) direction control (bitwise) s output latch stop drive write to pbfc write to pbcr reset internal data bus b selector a write to pb read pb pb7 (ta2in/int7/keyb) s ta2in tmp1942cy/cz port b register 7 6 5 4 3 2 1 0 pb bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (0xffff_f051) read/write r/w after reset input mode (output latch register set to 1) port b control register 7 6 5 4 3 2 1 0 pbcr bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c (0xffff_f054) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out input/output settings for port b 0 input 1 output port b function register 7 6 5 4 3 2 1 0 pbfc bit symbol pb7f pb6f pb5f pb4f pb3f pb2f pb1f pb0f (0xffff_f055) read/write w after reset 0 0 0 0 0 0 0 0 function 0:port 1:ta2in int7 keyb 0: port 1: ta3out 0: port 1: tb3out tb4in1 0: port 1: inte tb3in1 0: port 1: intd tb3in0 0: port 1: tb2out tb4in0 0: port 1: intc tb2in1 0: port 1: intb tb2in0 function corresponding pbfc bit corresponding pbcr bit port used select tb2in0 input 1 0 select intb input 1 (*1) 0 pb0 select tb2in1 input 1 0 select intc input 1 (*1) 0 pb1 select tb2out output 1 1 select tb4in0 input 0 1 pb2 select tb3in0 input 1 0 select intd input 1 (*1) 0 pb3 select tb3in1 input 1 0 select inte input 1 (*1) 0 pb4 select tb3out output 1 1 select tb4in1 input 0 1 pb5 select ta3out output 1 1 pb6 select ta2in input 1 0 select int7 input 1 0 select keyb input 1 0 pb7 (*1) set this bit when using the pin for a stop mode termination interrupt with syscr tmp1942cy/cz tmp1942cy/cz-97 3.5.11 port c (pc0-pc7) port c is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pccr is used to set the port for input or output . a reset clears pccr to 0 , putting port c in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pc0 , pc1 and pc2 function as 8 - bit timer input or external interrupt input , pc3 and pc5 as 8 - bit timer output , pc6 as 16 - bit timer input or key input , pc4 as 8 - bit timer input , and pc7 as 16 - bit timer input or 8 - bit timer output . these functions are enabled by setting the corresponding bits of pcfc to 1 . a reset clears pccr and pcfc to 0 , placing port c in input mode . pc6 has a pull - up resistor , which is enabled only when kwupcnt < pe > is set to 1 in the key on wake - up circuit and key input is enabled in kwupstn . for details , refer to the description of the key on wake - up function . when the pin is functioning as a port pin , its pull - up resistor is disabled . port c becomes a 5 v input / output port when 5 v is supplied to its dedicated power supply pin dvcc52 . it becomes a vcc - based ( 3 v ) port when vcc is supplied to dvcc52 . figure 3.5.29 port c (pc3, pc5) function control (bitwise) direction control (bitwise) s output latch stop drive write to pcfc ta5out ta7out write to pccr reset internal data bus s a selector b write to pc s b selector a timer f/f output read pc pc3 (ta5out) pc5 (ta7out) tmp1942cy/cz tmp1942cy/cz-98 figure 3.5.30 port c (pc0, pc1, pc2, pc6) function control (bitwise) direction control (bitwise) s output latch stop drive write to pcfc write to pccr reset internal data bus b selector a write to pc read pc pc0 (ta4in/int8) pc1 (ta6in/int9) pc2 (ta8in/inta) s ta4in, ta6in ta8in int8, 9, a keyc keymen pe selector y a b dpe tg fs function control (bitwise) direction control (bitwise) s output latch stop drive write to pcfc write to pccr reset internal data bus b selector a write to pc read pc pc6 (tb8in0/in0/keyc) s tb8in0 reset tmp1942cy/cz tmp1942cy/cz-99 figure 3.5.31 port c (pc7, pc4) function control (bitwise) direction control (bitwise) s output latch stop drive write to pcfc ta9out write to pccr reset internal data bus s a selector b write to pc s b selector a timer f/f output read pc pc7 (tb8in1/ta9out) tb8in1 function control (bitwise) direction control (bitwise) s output latch stop drive write to pcfc write to pccr reset internal data bus b selector a write to pc read pc pc4 (tain) s taain tmp1942cy/cz port c register 7 6 5 4 3 2 1 0 pc bit symbol pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (0xffff_f058) read/write r/w after reset input mode (output latch register set to 1) port c control register 7 6 5 4 3 2 1 0 pccr bit symbol pc7c pc6c pc5c pc4c pc3c pc2c pc1c pc0c (0xffff_f05a) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out port c control register 0 input 1 output port c function register 7 6 5 4 3 2 1 0 pcfc bit symbol pc7f pc6f pc5f pc4f pc3f pc2f pc1f pc0f (0xffff_f05b) read/write w after reset 0 0 0 0 0 0 0 0 function 0:port 1:tb8in ta9out 0: port 1: keyc tb8in0 0: port 1: ta7out 0: port 1: taain 0: port 1: ta5out 0: port 1: ta8in inta 0: port 1: ta6in int9 0: port 1: ta4in int8 function corresponding pcfc bit corresponding pccr bit port used select ta4in input 1 0 select int8 input need not be set 0 pc0 select ta6in input 1 0 select int9 input need not be set 0 pc1 select ta8in input 1 0 select inta input need not be set 0 pc2 select ta5out output 1 1 pc3 select taain input 1 0 pc4 select ta7out output 1 1 pc5 select tb8in0 input 1 0 select keyc input 1 0 pc6 select tb8in1 input 1 0 select ta9out output 1 1 pc7 note: for a pin to which two input functions are assigned in addition to the port function, use the control register for each function module to specify which function is used. figure 3.5.32 registers related to port c tmp1942cy/cz-100 tmp1942cy/cz tmp1942cy/cz-101 3.5.12 port d (pd0-pd7) port d is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pdcr is used to set the port for input or output . a reset clears pdcr to 0 , putting port d in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pd0 and pd3 function as 16 - bit timer input or sio data output , pd1 and pd4 function as 16 - bit timer input or sio data input , pd2 as sio serial clock input / output or cts * input , and pd5 as sio serial clock input / output , cts * input , or 16 - bit timer output . pd6 and pd7 can be connected to a low - frequency oscillator . these functions are enabled by setting the corresponding bits of pdfc1 to 1 . for pd5 , however , a combination of pdfc1 and pdfc2 determines whether it is used for a port , sio , or timer . the output open - drain control register ( pdode ) can be used to set pd0 , pd2 , pd3 and pd5 to open - drain output when they are used for output . pd6 and pd7 are always open - drain output when they are used for output . a reset clears pdcr , pdfc1 and pdfc2 to 0 , placing port d in input mode . figure 3.5.33 port d (pd0, pd3) function control (bitwise) direction control (bitwise) s output latch stop drive write to pdfc txd0 txd1 write to pdcr reset internal data bus s a selector b write to pd s b selector a read pd pd0 (tb9in0/txd0) pd3 (tbain0/txd1) tb9in0 tbain0 tmp1942cy/cz tmp1942cy/cz-102 figure 3.5.34 port d (pd1, pd4, pd2) function control (bitwise) direction control (bitwise) s output latch stop drive write to pdfc write to pdcr reset internal data bus b selector a write to pd read pd pd1 (rxd0/tb9in1) pd4 ( rxd1/tbain1 ) s tb9in1, tbain1 rxd0/1 function control (bitwise) direction control (bitwise) s output latch stop drive write to pdfc sclk output write to pdcr reset internal data bus write to pd read pd pd2 (sclk0/ cts0 ) cts0 sclk0 open-drain setting possible a selector b s b selector a s tmp1942cy/cz tmp1942cy/cz-103 figure 3.5.35 port d (pd5) note: the output mode is selected by a combinati on of pdfc1 and pdfc2. when pdfc1 tmp1942cy/cz tmp1942cy/cz-104 figure 3.5.36 port d (pd6, pd7) s direction control (bitwise) write to pd write to pdcr reset internal data bus read pd pd6 b y selector a s s output latch output buffer (open-drain output) s direction control (bitwise) write to pd write to pdcr read pd b y selector a s s output latch output buffer (open-drain output) low-frequency clock pd7 enable low-frequency oscillation (on with 1) tmp1942cy/cz port d register 7 6 5 4 3 2 1 0 pd bit symbol pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd (0xffff_f059) read/write r/w after reset input mode (output latch register set to 1) port d control register 7 6 5 4 3 2 1 0 pdcr bit symbol pd7c pd6c pd5c pd4c pd3c pd2c pd1c pd0c (0xffff_f05c) read/write w after reset 1 1 0 0 0 0 0 0 function 0: in 1: out input/output settings for port d 0 input 1 output port d function register 1 7 6 5 4 3 2 1 0 pdfc1 bit symbol ? ? pd5f pd4f pd3f pd2f pd1f pd0f (0xffff_f05d) read/write w after reset ? ? 0 0 0 0 0 0 function 0: port 1: sclk1/ cts1* 0: port 1: tbain1 rxd1 0: port 1: tbain0 txd1 0: port 1: sclk0/ cts0* 0: port 1: tb9in1 rxd0 0: port 1: tb9in0 txd0 port d function register 2 7 6 5 4 3 2 1 0 pdfc2 bit symbol ? ? pd5f2 ? ? ? ? ? (0xffff_f05e) read/write ? ? w ? ? ? ? ? after reset ? ? 0 ? ? ? ? ? function 0: port 1: tabout port d open-drain control register 7 6 5 4 3 2 1 0 pdode bit symbol ? ? pdode5 ? pdode3 pdode2 ? pdode0 (0xffff_f05f) read/write w after reset ? ? 0 ? 0 0 ? 0 function 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain tmp1942cy/cz-105 tmp1942cy/cz function corresponding pdfc1 bit corresponding pdfc2 bit corresponding pdcr bit port used select tb9in0 input 1 need not be set (no bit provided) 0 select txd0 output 1 need not be set (no bit provided) 1 pd0 select tb9in1 input 1 need not be set (no bit provided) 0 select rxd0 input 1 need not be set (no bit provided) 0 pd1 select sclk0 input 1 need not be set (no bit provided) 0 select sclk0 output 1 need not be set (no bit provided) 1 select cts0* input 1 need not be set (no bit provided) 0 pd2 select tbain0 input 1 need not be set (no bit provided) 0 select txd1 output 1 need not be set (no bit provided) 1 pd3 select tbain1 input 1 need not be set (no bit provided) 0 select rxd1 input 1 need not be set (no bit provided) 0 pd4 select sclk1 input 1 0 0 select sclk1 output 1 0 1 select cts1 input 1 0 0 select tabout output 0 1 1 pd5 note: for a pin to which two input functions are assi gned in addition to the port function, use the control register for each function module to specify which function is used. figure 3.5.37 registers related to port d tmp1942cy/cz-106 tmp1942cy/cz tmp1942cy/cz-107 3.5.13 port e (pe0-pe7) port e is an 8 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pecr is used to set the port for input or output . a reset clears pecr to 0 , putting port e in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pe0 and pe3 function as sio data output , pe1 and pe4 as sio data input , pe2 and pe5 as sio clk input / output or cts * input , and pe6 and pe7 as external interrupt input . these functions are enabled by setting the corresponding bits of pefc to 1 . a reset clears pecr and pefc to 0 , placing port e in input mode . the output open - drain control register ( peode ) can be used to set pe0 , pe2 , pe3 and pe5 to open - drain output when they are used for output . figure 3.5.38 port e (pe0, pe1) function control (bitwise) direction control (bitwise) s output latch stop drive write to pefc txd3/4 write to pecr reset internal data bus write to pe read pe pe0 (txd3) pe1 (txd4) open-drain setting possible a selector b s b selector a s tmp1942cy/cz tmp1942cy/cz-108 figure 3.5.39 port e (pe1, pe2, pe4, pe5) function control (bitwise) direction control (bitwise) s output latch stop drive write to pefc write to pecr reset internal data bus b selector a write to pe read pe pe1 (rxd3) pe4 (rxd4) s rxd1/4 function control (bitwise) direction control (bitwise) s output latch stop drive write to pefc sclk output 3 slk output 4 write to pecr reset internal data bus write to pe read pe cts3*, cts4* sclk3, sclk4 open-drain setting possible a selector b s b selector a s pe2 (sclk0/ 3cts ) pe5 (sclk1/ 4cts ) tmp1942cy/cz tmp1942cy/cz-109 figure 3.5.40 port e (pe6, pe7) function control direction control (bitwise) s output latch stop drive write to pe write to pecr reset internal data bus pe6 (int1) pe7 (int2) output buffer reset read pe int1, 2 tmp1942cy/cz port e register 7 6 5 4 3 2 1 0 pe bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (0xffff_f060) read/write r/w after reset input mode (output latch register set to 1) port e control register 7 6 5 4 3 2 1 0 pecr bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c (0xffff_f062) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out input/output settings for port e 0 input 1 output port e function register 7 6 5 4 3 2 1 0 pefc bit symbol pe7f pe6f pe5f pe4f pe3f pe2f pe1f pe0f (0xffff_f063) read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: int2 0: port 1: int1 0: port 1: sclk4/ cts4* 0: port 1: rxd4 0: port 1:itxd4 0: port 1: sclk3/ cts3* 0: port 1: rxd3 0: port 1: txd3 port e open-drain control register 7 6 5 4 3 2 1 0 peode bit symbol ? ? peode5 ? peode3 peode2 ? peode0 (0xffff_f066) read/write ? w ? w w ? w after reset ? ? 0 ? 0 0 ? 0 function 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain function corresponding pefc bit corresponding pecr bit port used select txd3 output 1 1 pe0 select rxd3 input 1 0 pe1 select sclk3 input 1 0 select sclk3 output 1 1 select cts3 input 1 0 pe2 select txd4 output 1 1 pe3 select rxd4 input 1 0 pe4 select sclk4 input 1 0 select sclk4 output 1 1 select cts4 input 1 0 pe5 select int1 input 1 (*1) 0 pe6 select int2 input 1 (*1) 0 pe7 *1 set this bit when using the pin for a stop mode termination interrupt with syscr tmp1942cy/cz tmp1942cy/cz-111 3.5.14 port f (pf0-pf6) port f is a 7 - bit general - purpose input / output port whose bits can each be set independently for input or output . the control register pfcr is used to set the port for input or output . a reset clears pfcr to 0 , putting port f in input mode . in addition to functioning as an input / output port , the pins of this port can also function as various input / output pins : pf0 functions as sio data output , pf1 as sio data input or key input , pf2 as sio clk input / output or cts * input , pf3 , pf4 and pf5 as sbi input / output , and pf6 as external interrupt input . these functions are enabled by setting the corresponding bits of pffc to 1 . a reset clears pfcr and pffc to 0 , placing port f in input mode . the output open - drain control register ( pfode ) can be used to set pf0 , pf2 , pf4 and pf5 to open - drain output when they are used for output . port f becomes a 5 v input / output port when 5 v is supplied to its dedicated power supply pin dvcc51 . it becomes a vcc - based ( 3 v ) port when vcc is supplied to dvcc51 . figure 3.5.42 port f (pf0) function control (bitwise) direction control (bitwise) s output latch stop drive write to pffc txd5 write to pfcr reset internal data bus write to pf read pf pf0 (txd5) open-drain setting possible a selector b s b selector a s tmp1942cy/cz tmp1942cy/cz-112 figure 3.5.43 port f (pf1) keyd keymen pe selector y a b dpe tg fs function control (bitwise) direction control (bitwise) s output latch stop drive write to pffc write to pfcr reset internal data bus b selector a write to pf read pf pf1 (rxd5/keyd) s rxd5 tmp1942cy/cz tmp1942cy/cz-113 figure 3.5.44 port f (pf2, pf3) function control (bitwise) direction control (bitwise) s output latch stop drive write to pffc sclk output write to pfcr reset internal data bus write to pf read pf pf2 (clk5/ cts5 ) cts5* sclk5 open-drain setting possible a selector b s b selector a s function control (bitwise) direction control (bitwise) s output latch stop drive write to pffc sclk output write to pfcr reset internal data bus write to pf read pf pf3 (sck) a selector b s b selector a s reset sck input tmp1942cy/cz tmp1942cy/cz-114 figure 3.5.45 port f (pf4, pf5) function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc so output write to pacr reset internal data bus write to pa read pa pf4(so/sda) open-drain setting possible a selector b s b selector a s reset sda input function control (bitwise) direction control (bitwise) s output latch stop drive write to pafc write to pacr reset so output internal data bus write to pa read pa pf5 (si/scl) open-drain setting possible cde tmp1942cy/cz tmp1942cy/cz-115 figure 3.5.46 port f (pf6) function control direction control (bitwise) s output latch stop drive write to pf write to pfcr reset internal data bus pf6 (int0) output buffer reset read pf int0 tmp1942cy/cz port f register 7 6 5 4 3 2 1 0 pf bit symbol ? pf6 pf5 pf4 pf3 pf2 pf1 pf0 (0xffff_f061) read/write r/w after reset input mode (output latch register set to 1) port f control register 7 6 5 4 3 2 1 0 pfcr bit symbol ? pf6c pf5c pf4c pf3c pf2c pf1c pf0c (0xffff_f064) read/write w after reset 0 0 0 0 0 0 0 0 function 0: in 1: out input/output settings for port f 0 input 1 output port f function register 7 6 5 4 3 2 1 0 pefc bit symbol ? pf6f pf5f pf4f pf3f pf2f pf1f pf0f (0xffff_f065) read/write w ? after reset ? 0 0 0 0 0 0 0 function 0: port 1: int0 0: port 1: si/scia 0: port 1: so/sda 0: port 1: sok 0: port 1: solk4 cots5 0: port 1: keyd rxd5 0: port 1: txd5 port f open-drain control register 7 6 5 4 3 2 1 0 peode bit symbol ? ? pfode5 pfode4 ? pfode2 ? pfode0 (0xffff_f067) read/write ? w ? w w ? w after reset ? ? 0 ? 0 0 ? 0 function 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain 0: cmos 1: open- drain function corresponding pffc bit corresponding pfcr bit port used select txd5 output 1 1 pf0 select rxd5 input 1 0 select keyd input 1 0 pf1 select sclk4 input 1 0 select sclk4 output 1 1 select cts5 input 1 0 pf2 select sck output 1 1 select sck input 1 0 pf3 select so/sda 1 1 pf4 select si/scl 1 1 pf5 select int0 input 1(*1) 0 pf6 *1 set this bit when using the pin for a stop mode termination interrupt with syscr tmp1942cy/cz tmp1942cy/cz-117 3.6 external bus interface the tmp1942 contains an external bus interface function which is necessary for connecting memory or i / os which are external to the chip . this function is implemented by the external bus interface circuit ( ebif ) and the cs ( chip select )/ wait controller . the cs / wait controller specifies mapping addresses for any four addre ss spaces, and controls a wait state and data bus width ( 8 bits or 16 bits ) for these four address spaces and other external address spaces. the external bus interface circuit ( ebif ) controls timing for the external bus based on settings made with the cs / wait controller . the ebif also controls dy namic bus sizing and the arbitration of bus contention with external bus masters . ? wait function can be set individually for each block . ? a wait state of up to 7 clock cycles can be automatically inserted . ? wait states can be inserted from the wait pin . ? data bus width the bus width can be independently selected as 8 bits or 16 bits for each block . ? read recovery cycle when a external bus cycle is immediately followed by a next external bus cycle, up to two dummy clock cycles can be inserted . insertion of the d ummy cycle ( s) can be set individually for each block . ? control of ale width the ale width can be set to 0 . 5 or 1 . 5 clock cycles. the set ale width applies to all blocks in common . ? arbitration of bus contention tmp1942cy/cz tmp1942-118 3.6.1 address and data pins (1) setting address and data pins for external memory connections , port 0 ( ad0 - ad7 ), port 1 ( ad8 - ad15 / a8 - a15 ) and port 2 ( a16 - a23 / a0 - a7 ) pins can be used as the address bus and the data bus . one of the following four bus configurations can be selected by setting up th e port registers . (1) (2) (3) (4) number of address bus lines max.24 (~16 mb) max.24 (~16 mb) max.16 (~64 kb) max.8 (~256 b) number of data bus lines 8 16 8 16 number of multiplexed address/data bus lines 8 16 0 0 port 0 ad0 ~ ad7 ad0 ~ ad7 ad0 ~ ad7 ad0 ~ ad7 port 1 a8 ~ a15 ad8 ~ ad15 a8 ~ a15 ad8 ~ ad15 port function port 2 a16 ~ a23 a16 ~ a23 a0 ~ a7 a0 ~ a7 timing diagram note 1: even for cases (3) and (4), addresses are output because the data bus pins are shared with the address bus. note 2: ports 0 to 2 are set for input after a re set, and do not function as address or data bus pins. note 3: any one of (1) to (4) can be selected by setting the p1cr, p1fc, p2cr and p2fc registers as desired. (2) address hold when an internal area is accessed when an internal area is accessed , the address bus retains the previous address which was output by the external area device ; thus the address does not change . in addition , the address/ data bus is placed in high - impedance state. a23~8 a23~8 a7~0 d7~0 ad7~0 ale rd a23~16 ad15~0 ale rd a23~16 a15~0 d15~0 (note1) a15~0 ad7~0 ale rd a15~0 a7~0 d7~0 a7~0 ad15~0 ale rd a7~0 a15~0 d15~0 (note1) tmp1942cy/cz tmp1942cy/cz-119 3.6.2 external bus operation this section explains various bus timings . in the following timing diagrams , the address bus is chosen to be a23 - a16 and the address / data bus is chosen to be ad15 - ad0 . (1) basic bus operation external bus cycles in the tmp1942 essentially consist of three clock cycles . a wait state can be in serted , as will be explained later . the basic clock for external bus cycles is the same as the internal system clock . figure 3.6.1 shows a read bus timing . figure 3.6.2 shows a write bus timing . during internal access, the address bus does not change , as shown in the diagram , nor doe s ale output a latch pulse . the address / data bus is placed in high - impedance state, and neither rd and wr nor other control signals are asserted . figure 3.6.1 read operation timing diagram figure 3.6.2 write operation timing diagram note: fsys expresses one period of share of system clock. a [23 : 16] a d [15 : 0] a le rd external access internal access enter hi-z state does not output ale does not output rd holds upper address adr data tsys tsys a [23 : 16] a d [15 : 0] a le wr external area internal area enter hi-z state does not output ale does not output wr holds upper address adr data tmp1942cy/cz tmp1942-120 (2) wait timing wait cycles can be inserted individually for each block by using the cs / wait controller . the following two types of wait insertion can be used : a . automatic wait insertion of up to 7 clock cycles b . wait insertion from wait pin note : ? please set the number of wait as ?+ 1 ? when you use = long and busrq the ale width .? timing diagrams with a wait state inserted are shown below . figure 3.6.3 read operation timing diagra m (with 0 wait cycles and 1 wait cycle) figure 3.6.4 read operation timing diagram (1+n wait cycles, n = 1) a [23 : 16] a d [15 : 0] a le rd upper address upper address adr data adr data 0 wait 1 wait wait tsys a [23 : 16] a d [15 : 0] a le rd upper address upper address adr data data wait 0 wait (1+ n wait, n = 1) wait tsys adr tmp1942cy/cz tmp1942cy/cz-121 figure 3.6.5 write operation timing diagra m (with 0 wait cycles and 1 wait cycle) figure 3.6.6 write operation timing diagram (1+n wait cycles, n = 1) a [23 : 16] a d [15 : 0] a le wr upper address upper address adr data adr data 0 wait 1 wait wait tsys a [23 : 16] a d [15 : 0] a le wr upper address upper address adr data data 0 wait (1+ n wait, n = 1) wait wait tsys adr tmp1942cy/cz tmp1942-122 (3) ale assertion time the ale assertion time can be selected as either 0 . 5 or 1 . 5 clock cycles. the bit for setting this assertion time is provided in the system clock control register . the default assertion time is 1 . 5 clock cycles. the assertion time cannot be set individually fo r blocks in the external area ; it applies universally to the entire external address space . note : ? please set the number of wait as ?+ 1 ? when you use = long and busrq the ale width .? figure 3.6.7 ale assertion time figure 3.6.8 shows read operation timing with an ale assertion time of 0 . 5 clock cycles and th at with an ale assertion time of 1 . 5 clock cycles. figure 3.6.8 read operation timing diagram (with ale asserted for 0.5 and 1.5 clock cycles) a le (alesel = 0) a d [15 : 0] (alesel = 1) a d [15 : 0] 0.5 clock cycle 1.5 clock cycles tsys a [23 : 16] a d [15 : 0] a le rd upper address upper address adr data adr data ale 0.5 clock cycle ale 1.5 clock cycles tsys tmp1942cy/cz tmp1942cy/cz-123 (4) read recovery time when an external access occurs after reading from an external area , a dummy cycle can be inserted to create a recovery time . dummy cycles can only be inserted when the immediately preceding cycle is a read cycle . external read followed by external read : can be inserted external read fo llowed by external write : can be inserted external write followed by external access: cannot be inserted the number of dummy cycles can be specified independently for each block as one clock cycle or two clock cycles. use the cs / wait controller to set the number of clock cycles. figure 3.6.9 rea d recovery time as shown above , by adding two dummy clock cycles, a sufficient time from the rise of rd to the output of the next address can be secured even when the device is operating at a fast clock speed . figure 3.6.10 shows a bus timing diagram where one and two dummy clock cycles are inserted . figure 3.6.10 read operation timing di agram (with dummy cycles inserted) read data rd a d [15 : 0] a le a le next adr two clock cycles added a d [15 : 0] read data next adr tsys adr a le a d [15 : 0] data adr a [23 : 16] dummy cycle (1 clock cycle) dummy cycles (2 clock cycles) rd tsys dummy upper address data dummy tmp1942cy/cz tmp1942-124 3.6.3 bus arbitration the tmp1942 allows external bus masters to be connected to the chip . two signals busrq and busak are used to arbitrate contention for bus control between the processor and external bus masters . external bus masters can only gain control of buses external to the tmp1942 . external bus masters cannot gain control of the device's internal bus . (1) access range for external bus masters external bus masters can on ly gain control of buses external to the tmp1942 . external bus masters cannot gain control of the device's internal bus ( g - bus ). therefore , external bus masters cannot access the device's internal memory and internal i / o blocks . contention for control of the external bus is arbitrated by the external bus in terface circuit ( ebif ); hence the cpu and the internal dmac are not involved in bus arbitration . even when an external bus master has control of the external bus , the cpu and the internal dmac can access the internal rom and ram and the internal registers . on the other hand , when the cpu or th e internal dmac attempts to access external memory while an external bus master has control of the external bus , the cpu or the internal dmac is kept waiting until the external bus master finishes control of the external bus . therefore , if busrq remains asserted for an excessive period of time , the tmp1942 may get locked . (2) gaining control of the bus an external bus master requests control of the bus from the tmp1942 by asserting the busrq signal . the tmp1942 samples the busrq signal during a break in the external bus cycles on the internal bus ( g - bus ) to determine whether or not to grant control of the bus . to give control of the bus to the external bus master , it asserts the busak signal . at the same time , it places the address bus , data bus and bus control signals in high - impedance state. if the data size to be loaded or stored is larger than the width of the bus for the external memory , multiple bus cycles may occur for a single data tran sfer ( bus sizing). in such a case , a break in the external bus cycles will occur when the last bus cycle has finished . the tmp1942 allows the insertion of dummy cycles when external access continues for successive bus cycles. even in this case it is only when a break in th e external bus cycles occurs on the internal bus ( g - bus ) that a request for bus control is accepted . during a dummy cycle the next external bus cycle is already activated on the internal bus , so that if the busrq signal is asserted during a dummy cycle , the bus will only be released after the next bus cycle has been completed . make sure the busrq signal remains asserted until control of the bus has been finished . figure 3.6.11 shows a timing sequence in which control of the bus is gained by an external bus master . note : ? please set the number of wait as ?+ 1 ? when you use = long and busrq the ale width .? tmp1942cy/cz tmp1942cy/cz-125 figure 3.6.11 timing at which control of the bus is gained (3) relinquishing control of the bus an external bus master relinquishes control of the bus in the following case : ? when it no longer requires control of the bus 1 ) relinquishing control of the bus when an external bus master no longer requires control of the bus . when th e external bus master no longer needs the control of the bus which it gained , it deasserts the busrq signal to return control of the bus to the tmp1942 . figure 3.6.12 shows a timing sequence in which the bus is released because the external bus master no longer requires control of it. figure 3.6.12 timing at which control of the bus is relinquished (1) (2) (3) internal address external address busrq busak tmp1942 external access tmp1942 external access external bus master cycle tmp1942 external access tsys tmp1942 external access (1) busrq is high. (2) the tmp1942 recognizes that busrq has been pulled low and releases the bus when the bus cycle has been completed. (3) the tmp1942 asserts busak upon completion of the bus cycle. the external bus master recognizes that busak has been asserted low and gains control of the bus, thereby initiating its bus operation. internal address external address busrq busak tmp1942 external access tmp1942 external access tmp1942 external access external bus master cycle tmp1942 external access (1) tsys (2)(3) (1) the external bus master has control of the bus. (2) because the external bus master no longer requires control of the bus, it deasserts busrq . (3) the tmp1942 recognizes that busrq has reverted to high and responds by deasserting busak . tmp1942cy/cz tmp1942-126 (4) bus release timings note: gaddr indicates the address on the g-bus. ad (addr) indicates the address on the address/data bus. addr indicates the address on the address bus. gaddr a d (addr) a dd r busrq busrq asserted during internal access (no external wait) busak internal external 2 external 1 exte r -nal 1 external 2 external 2 tsys gaddr a d (addr) a dd r busrq busrq asserted during internal access (no external wait) busak internal external 2 external 1 external 2 external 2 external 1 gaddr a d (addr) a dd r busrq busrq asserted during internal access (no external wait) busak internal external 2 external 1 external 1 external 2 external 2 tmp1942cy/cz tmp1942cy/cz-127 gaddr a d (addr) a dd r busrq busrq asserted during external access, foll owed by internal access (no external wait) busak external 1 external 2 internal external 2 external 1 external 1 external 1 external 2 gaddr a d (addr) a dd r busrq busrq asserted during external access, foll owed by internal access (no external wait) busak external 1 external 2 internal external 2 external 1 external 1 external 1 external 2 external 3 gaddr a d (addr) a dd r busrq busrq asserted during external access, foll owed by external access (no external wait) external 1 busak external 2 external 1 external 3 external 2 external 3 external 2 external 1 external 1 external 3 tmp1942cy/cz tmp1942-128 gaddr a d (addr) a dd r busrq bus sizing applied (no external wait) external 1 busak external 1 external 2 external 1a external 1b external 2 external 1a external 2 external 1b external 1b gaddr a d (addr) a dd r busrq bus sizing applied (no external wait) busak external 1a external 1d external 1c external 1 external 1a external 1b external 1c external 1d tmp1942cy/cz tmp1942cy/cz-129 gaddr a d (addr) a dd r busrq busrq asserted during external access, followed by internal access (no exter nal wait, 1 idle cycle) busak idle external 1 external 2 internal external 1 external 2 external 2 external 1 external 1 gaddr a d (addr) a dd r busrq busrq asserted during external access, followed by internal access (no exter nal wait, 1 idle cycle) busak idle external 1 external 2 internal external 1 external 2 external 1 external 1 external 2 external 3 gaddr a d (addr) a dd r busrq busrq asserted during external access, followed by external access (no external wait, 1 idle cycle) busak external 3 idle external 1 external 3 external 2 external 2 external 1 external 1 external 1 external 2 external 3 tmp1942cy/cz tmp1942-130 3.7 chip select/wait controller the tmp1942 supports direct connections to external devices ( i / o devices , rom and sram ). the tmp1942 provides four programmable chip select signals . programmable features include variable block sizes , data bus width , wait state insertion , and dummy cycle insertion for back - to - back bus cycles. 0cs - 3cs ( multiplexed with p40 - p43 ) are the chip select output pins for the cs0 - cs3 address ranges . these chip select signals are generated when the cpu or on - chip dmac issues an address within the programmed ranges . the p40 - p43 pins must be configured as cs0 - cs3 by programming the port 4 c ontrol ( p4cr ) register and the port 4 function ( p4fc ) register . chip select address ranges are defined in terms of a base address and an address mask . there is a base / mask address ( bman ) register for each of the four chip select signals , where n is a number from 0 to 3 . there is also a set of th ree chip select / wait control registers , b01cs , b23cs and bexcs , each of which consists of a master enable bit , a data bus width bit , a wait state field and a dummy cycle field . external memory devices can also use the wait pin to insert wait states and consequently prolong read and write bus cycles. 3.7.1 programming chip select ranges each of the four chip select address ranges is defined in the bman register . the basic chip select model allows one of the chip select output signals ( 0cs - 3cs ) to assert when an address on the address bus falls within a particular programmed range . the b01cs register defines specific operations for cs0 and cs1 , and the b23cs register defines specific operations for cs2 and cs3 ( see section 3 . 7 . 2 ). (1) base/mask address registers the organizations of the bman registers are shown in fig.3.7.1 and fig. 3.7.2. the base address (ban) field specifies the starting address for a ch ip select. any set bit in the address mask field ( man ) masks the corresponding base address bit. the address mask field determines the block size of a particular chip select line . the address is compared on every bus cycle. / base address the base address ( ban ) field specifies the upper 16 bits ( a31 - a16 ) of the starting addres s for a chip select . the lower 16 bits ( a15 - a0 ) are assumed to be zero . thus , the base address is any multiple of 64 kbytes starting at 0x0000 _ 0000 . figure 3 . 7 . 3 shows the relationships between starting addresses and the bman values . / address mask the address mask ( man ) field de fines whether any particular bits of the address should be compared or masked . any set bit masks the corresponding base address bit . the address compare logic uses only the address bits that are not masked ( i . e ., mask bit cleared to 0 ) to detect an address match . address bits that can be ma sked ( i . e ., supported block sizes ) differ for the four chip select spaces as follows : cs0 and cs1 spaces : a29 - a14 cs2 and cs3 spaces : a30 - a15 note : use physical addresses in the bman registers . tmp1942cy/cz tmp1942cy/cz-131 base / mask address registers bma0 ( 0xffff _ e400 ) to bma3 ( 0xffff _ e40c ) 7 6 5 4 3 2 1 0 bma0 bit symbol ma0 (0xffff_e400) read/write r/w after reset 1 1 1 1 1 1 1 1 function sets the size of the cs0 s pace. 0: used for comparing addresses 15 14 13 12 11 10 9 8 bit symbol ma0 read/write r/w after reset 0 0 0 0 0 0 1 1 function must always be set to 0. 23 22 21 20 19 18 17 16 bit symbol ba0 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a23-a16 for the start address. 31 30 29 28 27 26 25 24 bit symbol ba0 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a31-a24 for the start address. 7 6 5 4 3 2 1 0 bma1 bit symbol ma1 (0xffff_e404) read/write r/w after reset 1 1 1 1 1 1 1 1 function sets the size of the cs1 space. 0: used for comparing addresses 15 14 13 12 11 10 9 8 bit symbol ma1 read/write r/w after reset 0 0 0 0 0 0 1 1 function must always be set to 0. 23 22 21 20 19 18 17 16 bit symbol ba1 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a23-a16 for the start address. 31 30 29 28 27 26 25 24 bit symbol ba1 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a31-a24 for the start address. note: bits 10-15 in bma0 and bma1 must always be set to 0. this is because, although the cs0 and cs1 spaces can have a size of 16 kb to 1 gb, the tmp1942?s external address space is limited to 16 mb, which requires setting bits 10-15 to 0 so as not to mask the a24-a29 address bits. figure 3.7.1 base/mask addres s registers (bma0 and bma1) tmp1942cy/cz tmp1942-132 7 6 5 4 3 2 1 0 bma2 bit symbol ma2 (0xffff_e408) read/write r/w after reset 1 1 1 1 1 1 1 1 function sets the size of the cs2 s pace. 0: used for comparing addresses 15 14 13 12 11 10 9 8 bit symbol ma2 read/write r/w after reset 0 0 0 0 0 0 0 1 function must always be set to 0. 23 22 21 20 19 18 17 16 bit symbol ba2 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a23-a16 for the start address. 31 30 29 28 27 26 25 24 bit symbol ba2 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a31-a24 for the start address. 7 6 5 4 3 2 1 0 bma3 bit symbol ma3 (0xffff_e40c) read/write r/w after reset 1 1 1 1 1 1 1 1 function sets the size of the cs2 s pace. 0: used for comparing addresses 15 14 13 12 11 10 9 8 bit symbol ma3 read/write r/w after reset 0 0 0 0 0 0 0 1 function must always be set to 0. 23 22 21 20 19 18 17 16 bit symbol ba3 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a23-a16 for the start address. 31 30 29 28 27 26 25 24 bit symbol ba3 read/write r/w after reset 0 0 0 0 0 0 0 0 function sets a31-a24 for the start address. note: bits 9-15 in bma2 and bma3 must always be set to 0. this is because, although the cs2 and cs3 spaces can have a size of 32 kb to 2 gb, the tmp1942?s external address space is limited to 16 mb, which requires setting bits 9-15 to 0 so as not to mask the a24-a30 address bits. figure 3.7.2 base/mask addres s registers (bma2 and bma3) tmp1942cy/cz tmp1942cy/cz-133 figure 3.7.3 relationship between start a ddress and base address register values ( 2 ) setting the start address and address space size ? program the bma0 register as follows to cause cs0 to be asserted in the 64 kbytes of address space starting at 0xc000 _ 0000 . 31 1615 0 ba0 ma0 1 10 0 0 0 0 0 0000000000000000 0 0 0 0 0 011 c 0 0 0 0 0 0 3 bma0 register value the ba0 field specifies the upper 16 bits of the starting address , or 0xc000 . the ma0 field determines whether the a29 - a14 bits of the address should be compared or masked . the a31 and a30 bits are always compared . bits 15- 10 of the ma0 field must be cleared so that th e a29 - a24 bits are always compared . when the bma0 register is programmed as shown above , the a31 - a16 bits of the address are compared to the value of the ba0 field . consequently , the 64- kbyte address range between 0xc000 _ 0000 and 0xc000 _ ffff is defined as the 0cs space. base address value (ban) start address 0xffff_0000 0xffff_ffff ffff a ddress 0x0000_0000 64 kbytes 0x0006_0000 0006 0x0005_0000 0005 0x0004_0000 0004 0x0003_0000 0003 0x0002_0000 0002 0x0001_0000 0001 0x0000_0000 0000 tmp1942cy/cz tmp1942-134 ? program the bma2 register as follows to cause cs2 to be asserted in the 512 kbyte of address space starting at 0x1fc8 _ 0000 . 31 1615 0 ba2 ma2 0 00 1 1 1 1 1 1101000000000000 0 0 0 1 1 111 1 f d 0 0 0 1 f bma2 register value the ba2 field specifies the upper 16 bits of the starting address , or 0x1fc8 . the ma2 field determines whether the a30 - a15 bits of the address should be compared or masked . the a31 bit is always compared . bits 15 - 9 of the ma0 field must be cleared so that the a30 - a24 b its are always compared . when the bma2 register is programmed as shown above , the a31 - a19 bits of the address are compared to the value of the ba2 field . consequently , the 1 - mbyte address range between 0x1fc8 _ 0000 and 0x1fcf _ ffff is defined as the cs2 space. u pon reset , the cs0 , cs1 and cs3 spaces are disabled while the cs2 space is enabled and spans the entire 4 - gb address space. note: the tmp1942 does not assert any csn signal in the following address ranges: 0xffff_8000 through 0x1fff_bfff tmp1942cy/cz tmp1942cy/cz-135 (3) specifying the size of an address space table 3.7.1 shows the possible sizes of each cs space . if two or more address spaces are specified which overlap one another , the address space with the lowest cs space number will be selected since it has priority . example: the start address of the cs0 space is 0xc000_0000 and the space size is 16 kbytes. the start address of the cs1 space is 0xc000_0000 and the space size is 64 kbytes. table 3.7.1 cs spaces and their possible sizes 16 k 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m 16 m cs0 { { { { { { { { { { { cs1 { { { { { { { { { { { cs2 { { { { { { { { { { cs3 { { { { { { { { { { 0xc000_0000 0xc000_3fff 0xc000_0000 0xc000_3fff 0xc000_ffff cs1 space cs0 space when an address within the range of 0xc000_0000 to 0xc000_3fff is accessed, the cs0 space is selected. size (bytes) cs space tmp1942cy/cz tmp1942-136 3.7.2 chip select/wait control registers the chip select / wait control registers are shown in figure 3.7.4 to figure 3.7.6 . for each address space ( i . e ., the cs0 - cs3 spaces and any other address space ), the corresponding chip select / wait control register ( b01cs - b23cs or bexcs ) can be used to enable / disable the master , select a chip select out put waveform and data bus width , set the number of wait cycles and insert dummy cycles. if two or more address spaces are specified which overlap one another , the address space with the lowest cs space number will be selected since it has priority . ( the priority order is cs0 > cs1 > cs2 > cs3 > ex cs .) b01cs (0xffff_e480), b23cs (0x ffff_e484), bexcs (0xffff_e488) 7 6 5 4 3 2 1 0 b01cs bit symbol b0om ? b0bus b0w (0xffff_e480) read/write w ? w after reset 0 0 ? 0 0 1 0 1 function selects chip select output waveform. 00: rom/ram other settings are not allowed. selects data bus width. 0: 16 bits 1: 8 bits sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 7 cycles 1111: (1+n) cycles other settings are not allowed. 15 14 13 12 11 10 9 8 bit symbol ? ? ? ? b0e ? b0rcv read/write ? ? ? ? w ? ? after reset ? ? ? ? 0 ? 0 0 function cs0 enable 0: disable 1: enable sets the number of dummy cycles to be inserted. (read recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting not allowed 23 22 21 20 19 18 17 16 bit symbol b1om ? b1bus b1w read/write w ? w after reset 0 0 ? 0 0 1 0 1 function selects chip select output waveform. 00: rom/ram other settings are not allowed. selects data bus width. 0: 16 bits 1: 8 bits sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 7 cycles 1111: (1+n) cycles other settings are not allowed. 31 30 29 28 27 26 25 24 bit symbol ? ? ? ? b1e ? b1rcv read/write ? ? ? ? w ? w after reset ? ? ? ? 0 ? 0 0 function cs1 enable 0: disable 1: enable sets the number of dummy cycles to be inserted. (read recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting not allowed figure 3.7.4 chip selec t/wait control registers note : ? please set the number of wait as ?+ 1 ? when you use = long and busrq the ale width .? tmp1942cy/cz tmp1942cy/cz-137 7 6 5 4 3 2 1 0 b23cs bit symbol b2om ? b2bus b2w (0xffff_e484) read/write w ? w after reset 0 0 ? 0 0 1 0 1 function selects chip select output waveform. 00: rom/ram other settings are not allowed. selects data bus width. 0: 16 bits 1: 8 bits sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 7 cycles 1111: (1+n) cycles other settings are not allowed. 15 14 13 12 11 10 9 8 bit symbol ? ? ? ? b2e b2m b2rcv read/write ? ? ? ? w after reset ? ? ? ? 1 0 0 0 function cs2 enable 0: disable 1: enable selects cs2 space. 0: 4-gbyte space 1: cs space sets the number of dummy cycles to be inserted. (read recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting not allowed 23 22 21 20 19 18 17 16 bit symbol b3om ? b3bus b3w read/write w ? w after reset 0 0 ? 0 0 1 0 1 function selects chip select output waveform. 00: rom/ram other settings are not allowed. selects data bus width. 0: 16 bits 1: 8 bits sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 7 cycles 1111: (1+n) cycles other settings are not allowed. 31 30 29 28 27 26 25 24 bit symbol ? ? ? ? b3e ? b3rcv read/write ? ? ? ? w ? w after reset ? ? ? ? 0 ? 0 0 function cs3 enable 0: disable 1: enable sets the number of dummy cycles to be inserted. (read recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting not allowed note: the initial value of b23cs tmp1942cy/cz tmp1942-138 7 6 5 4 3 2 1 0 bexcs bit symbol bexom ? bexbus bexw (0xffff_e488) read/write w ? w after reset 0 0 ? 0 0 1 0 1 function selects chip select output waveform. 00: rom/ram other settings are not allowed. selects data bus width. 0: 16 bits 1: 8 bits sets the number of wait cycles 0000-0111: 0 cycles to 7 cycles 1111: (1+n) cycles other settings are not allowed. 15 14 13 12 11 10 9 8 bit symbol ? ? ? ? ? ? bexrcv read/write ? ? ? ? ? ? w after reset ? ? ? ? ? ? 0 0 function sets the number of dummy cycles to be inserted. (read recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting not allowed figure 3.7.6 chip selec t/wait control registers note : ? please set the number of wait as ?+ 1 ? when you use = long and busrq the ale width .? 3.7.3 example of use figure 3 . 7 . 7 shows an example of a tmp1942 system configuration with external memory connected . in this example a 128 - kbyte rom is connected with a data width of 16 bits and 256 - kbyte ram is connected with a data width of 16 bits . figure 3.7.7 example of external memory connec tion (rom width = 16 bits, ram width = 16 bits) when the tmp1942 is reset , the po rt 4 control register ( p4cr) and port 4 function register ( p4fc ) are both cleared to 0 , so that the cs signal output is disabled . to output a cs signal from this port , set the corresponding bits in these registers to 1 , first in p4fc and then in p4cr. latch 16 tmp1942 a15 - 16 upper byte a15 ram (128 kbits 8) ram (128 kbits 8) i/01 - 8 d0 - 7 d8 - 15 a1 - 15 a16 - 17 a1 - 15 a16 - 17 le d q am1 1cs ale rom (128 kbits 16) a16 a1 - 15 ad0 - 7 ad8 - 15 a16 - 17 a15 - 16 lower byte i/01 - 8 a0 - 14 oe w/r 1ce a0 - 14 oe ce am0 wr 2cs rd hwr a0 - 14 oe w/r 1ce tmp1942cy/cz 3.8 dma controller (dmac) the tmp1942 incorporates a four-channel dma controller. 3.8.1 features the dmac included in the tmp1942 has the following features: (1) independent 4-channel dma (2) two types of request for control of the bus: with snoop request or without snoop request (3) transfer request: internal transf er request: start by software external transfer request: request by interrupt (4) transfer mode: dual-address mode (5) transfer devices: memory-to-memory, memory-to-i/o, i/o-to-memory (6) device size: 32 bits for memory (16 or 8 bits can also be specified using the cs/wait controller); 8, 16 or 32 bits for i/o (7) address change: increment, decrement, fixed, irregular increment or irregular decrement (8) channel priority: fixed tmp1942cy/cz-139 tmp1942cy/cz tmp1942cy/cz-140 3.8.2 configuration 3.8.2.1 internal connections in the tmp1942 figure 3.8.1 shows how the dmac is connected internally within the tmp1942. figure 3.8.1 internal connection of dmac within the tmp1942 the dmac has four dma channels. these channels each receive a data transfer request signal (intdreqn) from the interrupt controlle r and return an acknowledge signal ( dackn ) in response to intdreqn. the letter ?n? denotes the channel number: 0 to 3. channel 0 has priority over channel 1, channel 1 has priority over channel 2 and channel 2 has priority over channel 3. the tx19 processor core has a snoop function. the snoop function entails the tx19 processor core releasing the core data bus to the dmac so that the dmac can access the internal rom or internal ram connected to the tx 19 processor core. the dmac can choose whether or not to use the snoop function. for details of the snoop function, refer to section 3.8.2.3 , ?snoop function?. there are two types of request for bus control: sreq and greq. the type which is selected depends on whether or not the dmac is using the snoop function. greq is used to request control of the bus when the snoop function is not in use and sreq is used to request control of the bus when the snoop function is in use. an sreq bus reques t has higher priority than a greq bus request. tx19 processor core address data indicate bus control relinquished control bus control request request release of bus control busgnt * busrel * intdreq [3 : 0]* dack [3 : 0]* dmac indicate bus control granted haveit * interrupt controller internal i/o interrupt request external interrupt request busreq * note * : internal signal note : dma channel priority exists only am ong those using the same type of bus request signal(sreq or greq).for example, once a given dma channel has acquired bus mastership using sreq, no other dma channel can assume bus mastership using greq until the ongoing dma transaction is completed. tmp1942cy/cz tmp1942cy/cz-141 3.8.2.2 internal blocks of the dmac figure 3.8.2 shows the internal blocks of the dmac. figure 3.8.2 internal blocks of the dmac 3.8.2.3 snoop function the tx19 processor core has a snoop function. this function is used to release the tx19 processor core?s data bus to the dmac. when the snoop function is activated, the tx19 processor core releases its data bus to the dmac. at the same time the tx19 processor core stops operating and remains idle until control of the data bus is returned to it by the dmac. since the dmac can access the processor?s internal ram or internal rom while the snoop function is active, th e ram or rom can be specified as the source or destination of a transfer. the tmp1942?s internal dmac can select whet her or not to use the tx19 processor core?s snoop function. if the dmac chooses to use the snoop function, it can then access the processor?s internal ram and internal rom. the cpu in the tx19 processor core will then be stalled until the dmac cancels the bus request. if the dmac chooses not to us e the snoop function, it cannot access the processor?s internal ram or internal rom. however, si nce in this case too the g-bus is released to the dmac, if the tx19 processor core attempts to access memory or i/o via the g-bus and the dmac does not respond to the request for release of bus control, th e tx19 processor core will not be able to execute bus operation, and as a result the pipeline will stall. note: when the snoop function is not used, the tx19 processor core does not release the data bus to the dmac. therefore, if the processor? s internal ram or internal rom is specified as the source or destination of a dma transfer, no acknowledge si gnal will be returned for the dmac?s transfer cycle, resulting in the bus being locked. channel 3 channel 2 ?? - ?? ? source ?? regisuter byte count ? ? status ? ? ? - ? 31 0 channel 1 source address register (sar0) 31 0 channel 0 destination address register (dar0) byte count register (bcr0) channel control register (ccr0) channel status register (csr0) dma transfer control register (dtcr0) dma control register(dcr) data holding register(dhr) tmp1942cy/cz tmp1942cy/cz-142 3.8.3 registers the dmac incorporates twen ty-six 32-bit registers. table 3.8.1 shows the dmac register map. table 3.8.1 dmac registers address register symbol register name 0xffff_e200 ccr0 channel control register (ch. 0) 0xffff_e204 csr0 channel status register (ch. 0) 0xffff_e208 sar0 source address register (ch. 0) 0xffff_e20c dar0 destination address register (ch. 0) 0xffff_e210 bcr0 byte count register (ch. 0) 0xffff_e218 dtcr0 dma transfer control register (ch. 0) 0xffff_e220 ccr1 channel control register (ch. 1) 0xffff_e224 csr1 channel status register (ch. 1) 0xffff_e228 sar1 source address register (ch. 1) 0xffff_e22c dar1 destination address register (ch. 1) 0xffff_e230 bcr1 byte count register (ch. 1) 0xffff_e238 dtcr1 dma transfer control register (ch. 1) 0xffff_e240 ccr2 channel control register (ch. 2) 0xffff_e244 csr2 channel status register (ch. 2) 0xffff_e248 sar2 source address register (ch. 2) 0xffff_e24c dar2 destination address register (ch. 2) 0xffff_e250 bcr2 byte count register (ch. 2) 0xffff_e258 dtcr2 dma transfer control register (ch. 2) 0xffff_e260 ccr3 channel control register (ch. 3) 0xffff_e264 csr3 channel status register (ch. 3) 0xffff_e268 sar3 source address register (ch. 3) 0xffff_e26c dar3 destination address register (ch. 3) 0xffff_e270 bcr3 byte count register (ch. 3) 0xffff_e278 dtcr3 dma transfer control register (ch. 3) 0xffff_e280 dcr dma control register (dmac) 0xffff_e28c dhr data-holding register (dmac) tmp1942cy/cz 3.8.3.1 dma control register (dcr) 31 30 16 rst w : type 0 : initial value 15 0 : type : initial value bit mnemonic field name description 31 rst reset reset (initial value: ?) resets the dmac by software. when the rst bit is set to 1, all of the dmac?s internal registers are reset to their initial values. also, all transfer requests are canceled and the four dma channels are turned off. 0: don?t care 1: initialize the dmac. figure 3.8.3 dma control register (dcr) note1: when the snoop request is disabled (ccrn.sreq=0) , a software reset of the dmac must be performed in the following sequence: 1. disable interrupts. 2. execute nop four times. 3. perform a software reset. 4. perform a software reset again. 5. re-enable interrupts. execute steps 3 and 4 consecutively. note 2: if the software reset command is written to the dcr register immediately after the completion of the last transfer cycle of a dma transaction, the dma-done inte rrupt will not be cleared. in this case, the software reset only initializes channel registers, etc. note 3: don?t issue a software reset comma nd to the dcr register via a dma transfer. tmp1942cy/cz-143 tmp1942cy/cz tmp1942cy/cz-144 3.8.3.2 channel control registers (ccrn) 31 30 25 24 23 22 21 20 19 18 17 16 0 str ? nien abien ? ? ? ? big ? w w r/w r/w r/w r/w r/w r/w r/w r/w : type 0 1 1 1 0 0 0 1 0 : initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sac dac trsiz dps ? exr pose lev sreq relen sio dio r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : type 0 0 0 0 0 0 0 00 0 00 00 00 : initial value bit mnemonic field name description 31 str channel start start (initial value: ?) starts channel operation. when this bit is set to 1, the channel enters ready state. data transfer can no w commence as soon as a transfer request is received. 1 is the only valid value which can be written to this bit; if a 0 is written, it is ignored. when read, this bit always appears to be 0. 1: start channel operation. 24 ? (reserved) this bit is reserved. make sure that it is always set to 0. 23 nien normal completion interrupt enable normal completion interrupt enable (initial value: 1) 1: enable normal completion interrupts. 0: disable normal completion interrupts. 22 abien abnormal completion interrupt enable abnormal completion interrupt enable (initial value 1) 1: enable abnormal completion interrupts. 0: disable abnormal completion interrupts. 21 ? (reserved) this bit is reserved. although th is bit is initially set to 1, make sure that it is always set to 0. 20 ? (reserved) this bit is reserved. make sure that it is always set to 0. 19 ? (reserved) this bit is reserved. make sure that it is always set to 0. 18 ? (reserved) this bit is reserved. make sure that it is always set to 0. 17 big big-endian big-endian (initial value: 1) 1: the channel operates in big endian mode. 0: the channel operates in little endian mode. on the tmp1942, set this bit to 0. 16 ? (reserved) this bit is reserved. make sure that it is always set to 0. 15 ? (reserved) this bit is reserved. make sure that it is always set to 0. 14 exr external request mode external request mode (initial value: 0) specifies the transfer request mode. 1: external transfer reques t (interrupt-driven start) 0: internal transfer request (soft start) 13 pose positive edge positive edge (initial value: 0) specifies the valid level for the transfer request signal intdreqn. this specification is effective only when the transfer request is an external transfer request (i.e., when the exr bit = 1). in the case of internal transfer requests (i.e., wh en the exr bit = 0) the value of pose is ignored. be sure to set the pose bit to 0 and the adjacent lev bit to 1 . figure 3.8.4 channel control registers (ccrn) (1/2) tmp1942cy/cz bit mnemonic field name description 12 lev level mode level m ode (initial value: 0) specifies the method for requesting external transfer. this specification is effective only when the transfer request is an external transfer request (i.e., when the exr bit = 1). in the case of internal transfer requests (i.e., when the exr bit = 0), the value of lev is ignored. be sure to set the lev bit to 1. 11 sreq snoop request snoop request (initial value: 0) specifies whether or not the snoop function is to be used as the bus control request mode. when the func tion is selected for use, the tx19 processor core?s snoop function is activated with the result that the dmac can use the processor core?s data bus. when the function is not selected for use, the tx19 processor core?s snoop function remains inactive. 1: the snoop function is used (i.e., the device is in sreq mode). 0: the snoop function is not used (i .e., the device is in greq mode). 10 relen bus control release request enable release request enable (i nitial value: 0) specifies whether the dmac will respond to requests for release of bus control issued from the tx19 processor core. this function is only effective in greq mode. in sreq mode, this function would have no effect sinc e the tx19 processor core cannot generate a request for release of bus control. 1: after the dmac has taken over bus control, it will respond to requests for release of bus cont rol. when the tx19 processor core issues a request for release of bu s control, the dmac will return control of the bus to the tx19 processor core when a break in bus operation occurs. 0: the dmac will not respond to req uests for release of bus control. 9 sio source i/o source type: i/o (initial value: 0) specifies the source device from which to perform transfer. 1: i/o device 0: memory 8 : 7 sac source address count source address count (initial value: 00) specifies the way in which the source address changes. 1x: the address is fixed. 01: the address is decremented. 00: the address is incremented. 6 dio destination i/o destination type: i/o (initial value: 0) specifies the destination device to which to perform transfer. 1: i/o device 0: memory 5 : 4 dac destination address count destination address count (initial value: 00) specifies the way in which the destination address changes. 1x: the address is fixed. 01: the address is decremented. 00: the address is incremented. 3 : 2 trsiz transfer size transfe r size (initial value: 00) indicates the amount of data to be transferred in response to one transfer request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1 : 0 dps device port size device port size (initial value: 00) specifies the bus width for the i/o device which has been specified as the source or destination device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) figure 3.8.4 channel control registers (ccrn) (2/2) tmp1942cy/cz-145 tmp1942cy/cz tmp1942cy/cz-146 3.8.3.3 channel status registers (csrn) 31 23 22 21 20 19 18 16 0 00 act nc abc ? bes bed conf r r/w r/w r/w r r r : type 0 0 0 0 0 0 0 : initial value 15 3 2 0 0 ? ? ?? r/w : type 000 : initial value bit mnemonic field name description 31 act channel active channel ac tive (initial value: 0) indicates whether the channel is in ready state. 1: channel is in ready state. 0: channel is not in ready state. 23 nc normal completion normal co mpletion (initial value: 0) indicates whether channel operation has terminated normally. if normal completion interrupts have been enabled by the ccr register, the dmac generates an interrupt request when this bit is set to 1. the nc bit can be cleared by writing a 0 to it. if a normal completion interrupt has been requested, the interrupt request is dropped when the nc bit is set to 0. if an attempt is made to set the str bit to 1 while the nc bit = 1, an error results. be sure to clear the nc bit to 0 before starting the next transfer. writing a 1 to this bit has no effect. 1: channel operation has terminated normally. 0: channel operation has not terminated normally. 22 abc abnormal completion abnormal completion (initial value: 0) indicates whether channel operation has terminated abnormally. if abnormal completion interrupts have been enabled by the ccr register, the dmac generates an interrupt request when this abc bit is set to 1. the abc bit can be cleared by writing a 0 to it. if an abnormal completion interrupt has been requested, the interrupt request is cancelled when the abc bit is set to 0. when the abc bit is cleared, the bes, bed and conf bits are also cleared to 0. if an attempt is made to set the str bit to 1 while the abc bit = 1, an error results. be sure to clear the abc bit to 0 before starting the next transfer. writing a 1 to this bit has no effect. 1: channel operation has terminated abnormally. 0: channel operation has not terminated abnormally. 21 ? (reserved) this bit is reserved. make sure that it is always set to 0. 20 bes source bus error source bus error (initial value: 0) 1: a bus error has occurred while the source was being accessed. 0: no bus error has occurred while the source was being accessed. 19 bed destination bus error destinat ion bus error (initial value: 0) 1: a bus error has occurred while destination was being accessed. 0: no bus error has occurred while destination was being accessed. 18 conf configuration error configur ation error (initial value: 0) 1: a configuration error has occurred. 0: no configuration error has occurred. 2 : 0 ? (reserved) these three bits are all reserv ed. always set all of these bits to 0. figure 3.8.5 channel st atus registers (csrn) tmp1942cy/cz 3.8.3.4 source address r egisters (sarn) 31 16 saddr r/w : type ? : initial value 15 0 saddr r/w : type ? : initial value bit mnemonic field name description 31:0 saddr source address source address (initial value: ?) sets the physical source address from which data will be transferred. after each transfer the address will change by the value specified in the dps bits of the ccrn register. figure 3.8.6 source ad dress registers (sarn) 3.8.3.5 destination address registers (darn) 31 16 daddr r/w : type ? : initial value 15 0 daddr r/w : type ? : initial value bit mnemonic field name description 31:0 daddr destination address destinat ion address (initial value: ?) sets the physical destinati on address to which data will be transferred. after each transfer the address will change by the value specified in the dps bits of the ccrn register. figure 3.8.7 destination address registers (darn) tmp1942cy/cz-147 tmp1942cy/cz tmp1942cy/cz-148 3.8.3.6 byte count registers (bcrn) 31 24 23 16 0 bc r/w : type ? : initial value 15 0 bc r/w : type ? : initial value bit mnemonic field name description 23:0 bc byte count byte count (initial value: ?) sets the number of bytes of data to be transferred. the amount by which the byte count is decremented after each transfer depends on the value specified in the trsiz bits of the ccrn register. figure 3.8.8 byte count registers (bcrn) 3.8.3.7 dma transfer control registers (dtcrn) 31 24 23 16 0 : type : initial value 15 5 3 2 0 0 dacm sacm r/w : type 000 000 : initial value bit mnemonic field name description 5 : 3 dacm destination address count mode destination address count mode specifies the mode used for c ounting the destination address. 000: count the address beginning at bit 0 of the address counter. 001: count the address beginning at bit 4 of the address counter. 010: count the address beginning at bit 8 of the address counter. 011: count the address beginning at bit 12 of the address counter. 100: count the address beginning at bit 16 of the address counter. 101: reserved 110: reserved 111: reserved 2 : 0 sacm source address count mode source address count mode specifies the mode used for counting the source address. 000: count the address beginning at bit 0 of the address counter. 001: count the address beginning at bit 4 of the address counter. 010: count the address beginning at bit 8 of the address counter. 011: count the address beginning at bit 12 of the address counter. 100: count the address beginning at bit 16 of the address counter. 101: reserved 110: reserved 111: reserved figure 3.8.9 dma transfer control registers (dtcrn) tmp1942cy/cz 3.8.3.8 data-holding register (dhr) 31 16 dot r/w : type ? : initial value 15 0 dot r/w : type ? : initial value bit mnemonic field name description 31 : 0 dot data on transfer data on transfer (initial value: ?) this is the data read from the source during a transfer in dual-address mode. figure 3.8.10 data-holding register (dhr) tmp1942cy/cz-149 tmp1942cy/cz tmp1942cy/cz-150 3.8.4 functions this section describes the functions of the dmac. 3.8.4.1 outline the dmac is a 32-bit dma controller capable of performing high-speed data transfers in a system incorporating the tx19 processor core without the need for any intervention by the tx19 processor core itself. (1) source and destination the dmac performs data transfers between one memory device and another or between a memory device and an i/o device. the device from which data is transferred is referred to as the source device and the device to which data is transferred is referred to as the destination device. both memory devices and i/o devices can be specified as the source and destination devices. however, the dmac can only transfer data from a memory device to an i/o device, from an i/o device to memory, or from memory to memory; it cannot transfer data between two i/o devices. the difference between memory devices and i/o devices resides in the methods by which the devices are accessed. when the dmac accesses an i/o device, it asserts the dackn signal. because only one dackn signal line is availa ble for each channel, the dmac can only perform one data transfer involv ing an i/o device at a time; hence the dmac cannot transfer data from one i/o device to another. an interrupt source can be specified for transf er requests to the dmac. when an interrupt occurs, the interrupt controller generates a requ est to the dmac. (in this case, no interrupt request to the tx19 processor core is generated. for details, refer to section 3.4, ?interrupts?.) this interrupt request from the interrupt controlle r is canceled by the da ckn signal. therefore, when an i/o device has been set as a transfer device, a request to the dmac is cancelled for each transfer performed (i.e., each time the am ount of data specified by the trsiz bits is transferred). on the other hand, in memory-to-memory transfers, dackn is asserted only when the number of bytes to be transferred (a s specified by the value of the bcrn register) falls to 0; hence several data transfers can be performed successively by a single transfer request. for example, when the dmac is transferring data between the tmp1942?s internal i/o and internal (or external) memory, although a transfer request from the internal i/o to the dmac is cancelled for each transfer performed, the dmac is kept waiting for the next transfer request unless the number of bytes to be transferred (a s specified by the value of the bcrn register) falls to 0. consequently, dma transfer is pe rformed successively until the bcrn register value is reduced to 0. tmp1942cy/cz (2) switching control of the bus (bus arbitration) when a transfer request is issued by the dmac s internal circuitry, the dmac requests control of the bus from the tx19 processor core. if an acknowledge signal is returned by the tx19 processor core, the dmac gains control of the bus and can perform data transfer bus cycles. the dmac can request two types of bus control: either bus control plus the use of the tx19 processor core s data bus (i.e., the snoop function), or bus control without the snoop function. this can be set independently for each channel in the corresponding register. the tx19 processor core may request release of bus control from the dmac. whether the dmac should respond to this request is set using independent register settings for each channel. however, this response function is effective only when the dmac does not request the snoop function (i.e., in greq mode). when the snoop function is requested (i.e., in sreq mode), the response function will have no eff ect because the tx19 pr ocessor core cannot generate requests for release of bus control in this mode. when there are no more transfer requests, the dmac will finish control of the bus. note1: the nmi interrupt is left pending while the dmac has control of the bus. note2: do not place the tmp1962 in halt powe r-down mode while the dmac is operating. (3) transfer request modes the dmac has two transfer request modes: in ternal transfer request mode and external transfer request mode. in internal transfer request mode, transfer re quests are generated internally in the dmac. a transfer request is generated by setting the start bit in one of the dmac s internal registers (the channel control register s str bit) to 1, upon which the dm ac will start a transfer operation. in external transfer request mode, transfer requ ests are generated by assertion of the transfer request signal (intdreqn), which is output by the interrupt controller after the start bit has been set to 1. the dmac can select level mode, in which a transfer request is generated on detection of a high- or low-level intdreqn signal, or edge mode, in which a transfer request is generated on detection of the rising or falling edge of the intdreqn signal. however, because the intdreqn signal in the tmp1942 is low-active, always make sure that the transfer request signal is set to be detected at low level. (4) address modes dual-address mode is the only address mode available for the dmac in the tmp1942. there is no single-address mode for the dmac. in dual-address mode, data transfers are performed between two memory devices or between memory and an i/o device. the addresses of the source and destination devices are output by the dmac. when accessing an i/o device, th e dmac asserts the dackn signal. in dual-address mode, the dmac executes two bus operations, one for reading and one for writing. the transfer data read from the sour ce device is temporarily stored in the dmac s internal data-holding register (dhr) before being written to the destination device. tmp1942cy/cz-151 tmp1942cy/cz tmp1942cy/cz-152 (5) channel operation the dmac has four channels (channels 0 to 3). each channel is activated by setting the start bit (str) in the channel control register (ccrn) to 1, so that the device enters ready state. when a transfer request occurs while a channel is in ready state, the dmac gains control of the bus and performs a data transfer. when th ere are no more transfer requests, the dmac finishes control of the bus, thereby entering ready state. when transfer for a channel is completed, the channel is placed in idle state. transfers may be terminated either normally or abnormally (for example, when an error occurs during transfer). an interrupt signal can be generated on completion of transfer. figure 3.8.11 is a state transition diagram for channel operations. figure 3.8.11 state transitions for channel operations (6) summary of transfer mode combinations the dmac can perform data transfers as fo llows according to the combination of mode settings. transfer request edge/level address mode transfer devices internal ? dual memory-to-memory memory-to-memory memory-to-i/o external low-level dual i/o-to-memory start transfer completed stop ready transfer bus control owned by dmac bus control not owned by dmac bus control not owned by dmac bus control owned by dmac tmp1942cy/cz (7) address change there are essentially three methods for changing the transfer address: increment, decrement or fixed. the method can be set independently for the source and destination addresses using the sac and dac bits in the ccrn register. if the transfer device is a memory device, increment, decrement or fixed may be specified. if the transfer device is an i/o device, only fixed may be specified. when an i/o device is sel ected as the source or destination device, be sure to set the sac and dac bits in the ccrn register to ?fixed?. if ?increment? or ?decrement? is selected as the address change method, the bit position at which counting begins can be set using the sacm and dacm bits in the dtcrn register. sacm corresponds to the source address and da cm the destination address. the bit position at which counting the address begins can be specified as bit 0, 4, 8, 12 or 16. selecting bit 0 results in normal increment or decremen t, increment or ir regular decrement. examples of how the address changes are shown below. example 1: when regular increment is sele cted for the source device and irregular increment is selected for the destination device sac: increment the address dac: increment the address trsiz: transfer in units of 32 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm = 000: count the address beginning at bit 0 of the address counter dacm = 001: count the address beginning at bit 4 of the address counter source destination first time 0xa000_1000 0xb000_0000 second time 0xa000_1004 0xb000_0010 third time 0xa000_1008 0xb000_0020 fourth time 0xa000_100c 0xb000_0030 example 2: when irregular decrement is selected for the source device and regular decrement is selected fo r the destination device sac: decrement the address dac: decrement the address trsiz: transfer in units of 16 bits source address: initial value 0xa000_1000 destination address: 0xb000_0000 sacm = 010: count the address beginning at bit 8 of the address counter dacm = 000: count the address beginning at bit 0 of the address counter source destination first time 0xa000_1000 0xb000_0000 second time 0x9fff_ff00 0xafff_fffe third time 0x9fff_fe00 0xafff_fffc fourth time 0x9fff_fd00 0xafff_fffa tmp1942cy/cz-153 tmp1942cy/cz tmp1942cy/cz-154 3.8.4.2 transfer requests for data to be transferred by the dmac, a transf er request must be generated and transmitted to the dmac. there are two types of dmac transfer re quests: internal transfer requests and external transfer requests. the transfer request type can be set individually for each channel. for either type of transfer reque st, when a transfer request occurs after channel operation has been activated, the dmac will gain control of the bus and perform data transfer. ? internal transfer requests a transfer request can be generated immediately by setting the str bit in the ccrn register to 1 while the exr bit in the same register = 0. this transfer request is referr ed to as an internal transfer request. in the case of an internal tran sfer request, because the transf er request remains active until channel operation has been completed, data tr ansfers will be performed successively unless transition to a higher priority channel occurs or until bus control is transferred to a higher priority bus master. internal transfer requests can only be used for transfers between memory and memory. ? external transfer requests a transfer request is generated when the interrupt controller is notified of a transfer request by the assertion of the intdreqn signal for a channel after the channel has been placed in ready state by setting the str bit of the ccrn register to 1 while the exr bit in the ccrn register = 0. this transfer request is referred to as an external transfer request. external transfer requests can be used for transfers between tw o memory devices and between memory and an i/o device. assertion of the intdreqn signal is recognized by detecting an edge or a level. the active edge or level is specified using the pose b it in the ccrn register. however, because the intdreqn signal in the tmp1942 is low-active, alwa ys make sure that the signal is set to be detected at low level. the amount of data to be transferred for one transfer request is specified using the trsiz field in the ccrn register. this can be specifi ed as 32 bits, 16 bits or 8 bits. transfer requests from the interrupt controller are cleared by assertion of the dackn signal. the dackn signal is asserted only when the number of bytes to be transferred during an i/o device bus cycle or a memory-to-memory transf er (as specified by the value of the bcrn register) falls to 0. consequently, for data transfer between memory and an i/o device intdreqn is cancelled every transfer request with the result that only one transfer is performed for the amount of data specified by trsiz. on the other hand, in memory-to-memory transfers, in tdreqn is not cancelled until the number of bytes to be transferred (as specified by the value of the bcrn register) falls to 0; hence several data transfers can be performed successively by a single transfer request. note that if an interrupt of the type specified for intdreqn is acknowledged by the dmac, but the interrupt is cleared by the interrupt controller or by another device before the dmac starts the dma transfer, one dma transfer ma y be performed after the interrupt has been cleared. tmp1942cy/cz 3.8.4.3 address modes the tmp 1942 only supports dual-address mode in which both the source and destination devices are explicitly addressed.. in dual-address mode the dmac first executes a r ead from the source device. the data read from the source device is temporarily stored in the dmac s internal register dhr. next, the dmac executes a write to the destination device to write this data to the destination device, thus performing a data transfer from the source to the destination device. although bit 15 of the ccrn register in the tmp1 942 can be used to specify the address mode, this bit must always be set to 0 because the tmp1942 only suppor ts dual-address mode. dmac destination device data data bus (1) address (2) (2) (1) address bus source device figure 3.8.12 diagram of data transfer in dual-address mode tmp1942cy/cz-155 tmp1942cy/cz tmp1942cy/cz-156 figure 3.8.13 diagram of data transfer in single-address mode ? dual-address mode i n dual-address mode, a data transfer is executed using two bus operations: -read operation, in which the dmac outputs the ad dress of the source device, reads data from the source device and stores the data in its internal register dhr -write operation, in which the dmac outputs the address of the des tination device and writes the stored data from dhr to the destination device in dual-address mode, three types of transfers can be performed: -memory-to-memory -memory-to-i/o device -i/o device-to-memory the units of data transfer performed by the dmac are equal to the amount of data (32 bits, 16 bits or 8 bits) specified in the trsiz field of the ccrn register. this amount of data is transferred each time a transf er request is recognized. in dual-address mode, an amount of data equal to the transfer unit is read from the source device into the dhr register, then the data is written from the dhr register to the destination device. memory accesses occur at intervals equal to the unit of data transfer which has been set. when external memory is accessed, if the transf er unit is 32 bits and the bus width set by the cs/wait controller is 16 bits, then two 16-bit accesses will occur. si milarly, if the transfer unit is 32 bits and the bus width set by the cs/wait controller is 8 bits, then four 8-bit accesses will occur. data bus address bus dmac destination device (memory) data dack address source device (i/o) tmp1942cy/cz for memory-to-i/o device or i/o device-to-memory data transfers, the bus width of the i/o device (the device port size) needs to be set (to 32 bits, 16 bits or 8 bits) using the dps field in the ccrn register, in addition to the unit of data transfer. if the unit of data transfer and the device port size are equal, the dmac will perform one read or write operation for the i/o device. if the device port size is smaller than the unit of data transfer, the dmac will perform multiple read or write operations for the i/o device. for example, when performing a transfer to memory from an i/o device whose device port size is 8 bits when the unit of data transfer is 32 bits, the dmac will read data from the i/o device and store it in the dhr register four times, 8 bits at a time, and then write 32 bits of data from the dhr register to memory in one operation (or in two operations if the external memory s data bus is 16 bits wide). the source and destination addresses change at intervals equal to the unit of data transfer. the value of the bcrn register also changes by an amount equal to the unit of data transfer. the device port size cannot be set to a valu e greater than the unit of data transfer. table 3.8.2 summarizes the above information: table 3.8.2 unit of data transfer and device port size (dual-address mode) trsiz dps number of bus operations performed on i/o device 0x (32 bits) 0x (32 bits) once 0x (32 bits) 10 (16 bits) twice 0x (32 bits) 11 (8 bits) four times 10 (16 bits) 0x (32 bi ts) setting prohibited 10 (16 bits) 10 (16 bits) once 10 (16 bits) 11 (8 bits) twice 11 (8 bits) 0x (32 bi ts) setting prohibited 11 (8 bits) 10 (16 bi ts) setting prohibited 11 (8 bits) 11 (8 bits) once note: the dmac does not incremnt or decrement the address for i/o peripherals. therefore, if, for example, trsiz is programmed to 16 bits and dps is programmed to 8 bits, both the first and second bus cycles access the lower eight bits of the i/o data bus. tmp1942cy/cz-157 tmp1942cy/cz tmp1942cy/cz-158 3.8.4.4 channel operations a chann el is activated when the str bit in the ccr n register for the channel is set to 1. when a channel is activated, it is checked for errors; if no error is found, it is placed in ready state. if a transfer request occurs while a channel is in ready state, the dmac gains control of the bus and starts a tran sfer operation. channel operation may terminate normally or a bnormally, for example, when operation is forcibly terminated or terminated by an error. this status is indicated by the csrn register. (1) starting channel operation a channel is activated when the str bit in th e ccrn register for the channel is set to 1. when a channel is activated, it is checked for a configuration erro r; if no error is found, it is placed in ready state. if an error is detected , the channel operation terminates abnormally. when a channel is placed in ready state, the act b it in the csrn register fo r the channel is set to 1. if internal transfer requests have been set for the channel, a transfer request will be generated immediately, upon which the dmac will gain cont rol of the bus and start a data transfer. if external transfer requests have been set for the channel, a transfer requ est will be generated by assertion of intdreqn, upon which the dmac w ill gain control of the bus and start a data transfer. (2) terminating channel operation channel operation may terminate either normally or abnormally. this st atus is indicated in the csrn register. if an attempt is made to set the str bit in the ccrn register to 1 while the nc bit or abc bit of the csrn register = 1, channel operatio n will not start and will terminate abnormally. normal termination channel operation terminates normally in the following case. note that, in this case, transfer will always terminate after the dmac has finished transferring an amount of data equal to the unit of data transfer (the value set in the trsiz field of the ccrn register). ? when data transfer has been completed after the value of the bcrn register has fallen to 0 abnormal termination data transfers by the dmac may terminate abnormally in the following cases: ? termination due to configuration errors a configuration error is an error in the dma transfer settings. since a configuration error occurs before the dmac starts data tr ansfer operation, the sarn, darn and bcrn register values will remain as set. when operation for a channel terminates abnormally due to a configuration error, the conf bit in the csrn register is set to 1 at the same time that the abc bit is set to 1. causes of co nfiguration errors are shown below. -both sio and dio are set to 1. -the ccrn str bit is set to 1 when the nc bit or abc bit in the csrn register = 1. tmp1942cy/cz -a value which cannot be divided by the unit of data transfer is set in the bcrn register. -values which cannot be divided by the unit of data transfer are set in the sarn and darn registers. -an illegal combination of the device port size and data transfer unit has been set. -the str bit in the ccrn register is set to 1 while the bcrn register = 0. ? termination due to bus errors w hen transfer terminates abnormally due to a bus error, the bes or bed bit in the csrn register is set to 1 at the same time that the abc bit in the csrn register is set to 1. -the cpu is notified that a bus erro r has occurred during data transfer. 3.8.4.5 channel priority the dmac has four channels. a channel with a lo wer channel number always has higher priority. therefore, if transfer requests occur for channe ls 0 and 1 simultaneously, the dmac will perform the transfer operation for channel 0 s transfer request first. when there are no more transfer requests for channel 0, if the transfer request for channe l 1 is still in effect, the dmac will perform the transfer operation on channe l 1. (for internal transfer requests, th e transfer request is held unless it is cleared. for external transfer requ ests, this depends on the active state which has been set for the interrupt request assigned to dma requests by the interrupt controller. if the active state is set to edge mode, the transfer request will be held by the in terrupt controller. however, if the active state is set to level mode, the interrupt controller will not hold the transfer request. therefore, if level mode is set, the interrupt request signal must be kept asserted until it is recognized by the dmac.) if a transfer request for channel 0 occurs while da ta transfer on channel 1 is under way, a channel transition will occur. the data tr ansfer on channel 1 will be su spended and the dmac will start transfer on channel 0. when there are no more transfer request for channel 0, the dmac will resumes the transfer operation on channel 1. channel transition occurs when the dmac has finished transferring an amount of data equal to the unit of data transfer. in dual- address mode, this is when the dmac has finished writing all the stored data from the dhr register to the destination device. 3.8.4.6 interrupts the dma c can generate an interrupt request to the tx19 processor core on completion of channel operation. there are two ty pes of interrupts which can be requested in this case: normal completion interrupt and abnormal completion interrupt. ? normal completion interrupt w hen channel operation terminates normally, the nc bit in the csrn register is set to 1. at this time, if normal completion interrupts have been enabled using the nien bit in the ccrn register, an interrupt request to th e tx19 processor core is generated. ? abnormal completion interrupt w hen channel operation terminates abnormally, the abc bit in the csrn register is set to 1. at this time, if abnormal completion interrupts have been enabled by the abien bit in the ccrn register, an interrupt request to th e tx19 processor core is generated. tmp1942cy/cz-159 tmp1942cy/cz tmp1942cy/cz-160 3.8.4.7 endian mode if the unit of data transfer and the device port size are not equal in dual-address mode, the dmac will assemble or disassemble data in the dhr register. for example, if the source device is an i/o device whose port size is 8 bits while the destination device is a memory device, and the unit of data tran sfer is 32 bits, the dmac reads data from the i/o device four times and assembles it into 32 bits of data in the dhr register before writing it to memory. for example, the diagram below shows the relationship between an 8-bit i/o device and a 32-bit dhr register. the tmp1942 supports only little-endian data alignment. figure 3.8.14 data packing and unpacking d c b a 4n + 0 4n + 1 4n + 2 4n + 3 i/o device 8 0 big endian 31 0 dhr little endian 31 0 d c b a a b c d tmp1942cy/cz tmp1942cy/cz-161 3.8.5 operation dmac operations are synchronized to the rising edges of sysclk. 3.8.5.1 dual-address mode ? memor y-to-memory transfer figure 3.8.15 shows a timing example for one transfer session when 16-bit data is being transferred from external memory (which is 16 bits wide) to external memory (which is also 16 bits wide). although it is not shown here, data is transferred successively until the value of the bcrn register falls to 0. figure 3.8.15 dual-address mode (memory to memory) ? memory-to-i/o device transfer figure 3.8.16 shows a timing example for memory-to-i/o device transfer for cases where the unit of data transfer and the device port size ar e set to 16 bits and 8 bits, respectively. figure 3.8.16 dual-address mode (memory to i/o device) addr a [23 : 16] 0cs rd wr / whr ad [15 : 0] read write data addr data 1cs tsys addr a [23 : 16] 0cs rd wr ad [15 : 0] read write data addr data 1cs write addr data tsys tmp1942cy/cz tmp1942cy/cz-162 ? i/o device-to-memory transfer figure 3.8.17 shows a timing example for i/o device-to -memory transfer for cases where the unit of data transfer and the device port size ar e set to 16 bits and 8 bits, respectively. figure 3.8.17 dual-address mode (i/o device to memory) addr a [23 : 16] 0cs rd wr / whr ad [15 : 0] read read data 1cs write addr data addr data tsys tmp1942cy/cz example: dma transfer of serially r eceived data (scnbuf) to internal ram example dma settings ? channel used: 0 ? source address: sc1buf ? destination: 0xffff_9800 (physical address) ? number of bytes transferred: 256 example serial channel settings ? data length: 8 bits, uart ? serial channel: channel 1 ? transfer rate: 9600 bps dma (channel 0) is used for transfer. dma0 is activated by an interrupt received on sio1. dma0 settings dcr 0x8000_0000 /* reset dma * / imcfl 15 7 0 xxxx, xxxx, xx10, x100 /* level = 4 (arbitrary value) * / intclr 0x3c /* value of ivr [9:4] * / dtcr0 0x0000_0000 /* dacm = 000 * / /* sacm = 000 * / sar0 0xffff_f208 /* physical address of sc1buf * / dar0 0xffff_9800 /* physical address of destination * / bcr0 0x0000_00ff /* 256 (number of bytes to be transferred) * / ccr0 0x80c0_5b0f (contents) 31 27 23 19 1 000000011000 0 0 0 15 11 7 3 0 1011 x 11 x 0001 1 1 1 sio channel 1 settings imcch 31 15 xxxx, xxxx, xx11, 1000 /* assign to dmc0 activation source * / intclr 0x32 /* ivr [9:4], intrx1 interrupt source * / sc1mod0 0x29 /* uart mode, 8-bit length, baud rate generator * / sc1cr 0x00 br1cr 0x1d /* @fc = 32 mhz (approx. 9615 bps) * / tmp1942cy/cz-163 tmp1942cy/cz tmp1942cy/cz-164 3.9 8-bit timers (tmra) the tmp1942 contains twelve 8-b it timer channels (tmra0-tmrab). there are six tmra modules, referred to as tmra01, tmra23, tmra45, tmra67, tmra89 and tmraab, each of which is comprised of two channels. each module can operate in the following four modes: ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave output mode (ppg: variable duty with variable cycle) ? 8-bit pulse width modulation output mode (pwm: variable duty with constant cycle) figure 3.9.1 shows a block diagram of tmra01. each channel consists primarily of an 8-bit up-counter, an 8- bi t comparator and an 8-bit timer register. each pair of channels also incorpor ates one prescaler and one timer flip-flop. timer operation modes and f lip-flops are controlled by five registers. the six modules (tmra01, tmra23, tmra45, tmra67, tmra89 and tmraab) operate independently of each other. because each module functions the same way except for a few differences as shown in tables table 3.9.1 and table 3.9.2, operation of the tmra01 only is described here. t able 3.9.1 s pecification differences among the tmra modules module specification tmra01 tmra23 tmra45 external clock input pin ta0in (shared with pa7) ta2in (shared with pb7) ta4in (shared with pc0) external pins timer flip-flop output pin ta1out (shared with pa6) ta3out (shared with pb6) ta5out (shared with pc3) timer run register ta01run (0xffff_f100) ta23run (0xffff_f108) ta45run (0xffff_f110) timer registers ta0reg (0xffff_f102) ta1reg (0xffff_f103) ta2reg (0xffff_f10a) ta3reg (0xffff_f10b) ta4reg (0xffff_f112) ta5reg (0xffff_f113) timer mode register ta01mod (0xffff_f104) ta23mod (0x ffff_f10c) ta45mod (0x ffff_f114) sfr name (address) timer flip-flop control register ta1ffcr (0xffff_f105) ta3ffcr (0xffff_f10d) ta5ffcr (0xffff_f115) table 3.9.2 specification differences among the tmra modules module specification tmra67 tmra89 tmraab external clock input pin ta6in (shared with pc1) ta8in (shared with pc2) taain (shared with pc4) external pins timer flip-flop output pin ta7out (shared with pc5) ta9out (shared with pc7) tabout (shared with pd5) timer run register ta67run (0xffff_f118) ta89run (0xffff_f120) taabrun (0xffff_f128) timer registers ta6reg (0xffff_f11a) ta7reg (0xffff_f11b) ta8reg (0xffff_f122) ta9reg (0xffff_f123) taareg (0xffff_f12a) tabreg (0xffff_f12b) timer mode register ta67mod (0x ffff_f11c) ta89mod (0x ffff_f124) t aabmod (0xffff_f12c) sfr name (address) timer flip-flop control register ta7ffcr (0xffff_f11d) ta9ffcr (0xffff_f125) tabffcr (0xffff_f12d) tmp1942cy/cz tmp1942cy/cz-165 3.9.1 block diagram of each module only a block diagram of tmra01 is described here. it applies to all other modules with the exception of differences in register, signal and other element names. figure 3.9.1 tmra01 block d iagram run/clear prescaler clock: t0 ta0trg external clock input: ta0in ta01mod tmp1942cy/cz tmp1942cy/cz-166 3.9.2 functional description of each circuit (1) prescaler the tmp1942 has a 9-bit prescaler to supply a clock to tmra01. the prescaler?s input clock t0 has a frequency of fperiph, fperiph/2 or fperiph/4 as selected by syscr0 tmp1942cy/cz tmp1942cy/cz-167 (2) up-counters (uc0 and uc1) uc0 and uc1 are 8-bit binary counters which count up synchronously with the input clock selected in timer mode register ta01mod. the input clock for uc0 is either the external cloc k entered via the ta0in pin or one of the three prescaler output clocks, t1, t4 or t16, according to the value set in ta01mod tmp1942cy/cz tmp1942cy/cz-168 figure 3.9.2 structure of timer register 0 (ta0reg) note: when data is written to ta0reg, the same address is allocated to the timer register and the register buffer. when tmp1942cy/cz tmp1942cy/cz-169 3.9.3 register description tmra01 run register 7 6 5 4 3 2 1 0 bit symbol ta0rde ? ? ? i2ta01 ta01prun ta1run ta0run read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable idle 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2ta01: operation in idle mode ta01prun: operation of the prescaler ta1run: operation of timer 1 ta0run: operation of timer 0 note: ta01run bits 4, 5 and 6 are undefined when read. tmra23 run register 7 6 5 4 3 2 1 0 bit symbol ta2rde ? ? ? i2ta23 ta23prun ta3run ta2run read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable idle 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2ta23: operation in idle mode ta23prun: operation of the prescaler ta3run: operation of timer 3 ta2run: operation of timer 2 note: ta23run bits 4, 5 and 6 are undefined when read. figure 3.9.3 tmra registers this bit controls the ta0reg double-buffer. 0 disable 1 enable ta23run (0xffff_f108) this bit controls the ta2reg double-buffer. 0 disable 1 enable ta01run (0xffff_f100) tmp1942cy/cz tmp1942cy/cz-170 tmra45 run register 7 6 5 4 3 2 1 0 bit symbol ta4rde ? ? ? i2ta45 ta45prun ta5run ta4run read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable i d l e 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2ta45: operation in idle mode ta45prun: operation of the prescaler ta5run: operation of timer 5 ta4run: operation of timer 4 note: ta45run bits 4, 5 and 6 are undefined when read. tmra67 run register 7 6 5 4 3 2 1 0 bit symbol ta6rde ? ? ? i2ta67 ta67prun ta7run ta6run read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable i d l e 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2ta67: operation in idle mode ta67prun: operation of the prescaler ta7run: operation of timer 7 ta6run: operation of timer 6 note: ta67run bits 4, 5 and 6 are undefined when read. figure 3.9.4 tmra registers ta45run (0xffff_f110 ) this bit controls the ta4reg double-buffer. 0 disable 1 enable this bit controls the ta6reg double-buffer. 0 disable 1 enable ta67run (0xffff_f118) tmp1942cy/cz tmp1942cy/cz-171 tmra89 run register 7 6 5 4 3 2 1 0 bit symbol ta8rde ? ? ? i2ta89 ta89prun ta9run ta8run read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable i d l e 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2ta89: operation in idle mode ta89prun: operation of the prescaler ta9run: operation of timer 9 ta8run: operation of timer 8 note: ta89run bits 4, 5 and 6 are undefined when read. tmraab run register 7 6 5 4 3 2 1 0 bit symbol taarde ? ? ? i2taab taabprun tabrun taarun read/write r/w ? ? ? r/w after reset 0 ? ? ? 0 0 0 0 function double buffer 0: disable 1: enable i d l e 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count i2taab: operation in idle mode taabprun: operation of the prescaler tabrun: operation of timer b taarun: operation of timer a note: taabrun bits 4, 5 and 6 are undefined when read. figure 3.9.5 tmra registers this bit controls the ta8reg double-buffer. 0 disable 1 enable this bit controls the taareg double-buffer. 0 disable 1 enable ta89run (0xffff_f120 ) taabrun (0xffff_f128) tmp1942cy/cz tmp1942cy/cz-172 tmra01 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm0 0 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra1 source clock 00: ta0trg 01: t1 10: t16 11: t256 tmra0 source clock 00: ta0in pin input 01: t1 10: t4 11: t16 00 external input (ta0in pin input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta01mod tmp1942cy/cz tmp1942cy/cz-173 tmra23 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm0 0 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 tmra3 source clock 00: ta2trg 01: t1 10: t16 11: t256 tmra2 source clock 00: ta2in pin input 01: t1 10: t4 11: t16 00 external input (ta2in pin input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta23mod tmp1942cy/cz tmp1942cy/cz-174 tmra45 mode register 7 6 5 4 3 2 1 0 bit symbol ta45m1 ta45m0 pwm41 pwm4 0 ta5clk1 ta5clk0 ta4clk1 ta4clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra5 source clock 00: ta4trg 01: t1 10: t16 11: t256 tmra4 source clock 00: ta4in 01: t1 10: t4 11: t16 00 ta4in 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta45mod tmp1942cy/cz tmp1942cy/cz-175 tmra67 mode register 7 6 5 4 3 2 1 0 bit symbol ta67m1 ta67m0 pwm61 pwm6 0 ta7clk1 ta7clk0 ta6clk1 ta6clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra7 source clock 00: ta6trg 01: t1 10: t16 11: t256 tmra6 source clock 00: ta6in 01: t1 10: t4 11: t16 00 ta6in 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta67mod tmp1942cy/cz tmp1942cy/cz-176 tmra89 mode register 7 6 5 4 3 2 1 0 bit symbol ta89m1 ta89m0 pwm81 pwm8 0 ta9clk1 ta9clk0 ta8clk1 ta8clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra9 source clock 00: ta8trg 01: t1 10: t16 11: t256 tmra8 source clock 00: ta8in 01: t1 10: t4 11: t16 00 ta8in 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) ta89mod tmp1942cy/cz tmp1942cy/cz-177 tmraab mode register 7 6 5 4 3 2 1 0 bit symbol taabm1 taabm0 pwma1 pwma0 tabclk1 tabclk0 taaclk1 taaclk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm pwm cycle 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmrab source clock 00: taatrg 01: t1 10: t16 11: t256 tmraa source clock 00: taain 01: t1 10: t4 11: t16 00 taain 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) taabmod tmp1942cy/cz tmp1942cy/cz-178 tmra1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taff1c1 taff1c0 taff1ie taff1is read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert ta1ff value (soft inversion). 01: set ta1ff to 1. 10: clear ta1ff to 0. 11: don?t care (these bits are always 11 when read.) controls ta1ff inversion. 0: disable inversion. 1: enable inversion . selects ta1ff inversion signal. 0: tmra0 1: tmra1 0 inverted by tmra0 1 inverted by tmra1 note: ta1ffcr bits 4, 5, 6 and 7 are undefined when read. tmra3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taff3c1 taff3c0 taff3ie taff3is read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert ta3ff value (soft inversion). 01: set ta3ff to 1. 10: clear ta3ff to 0. 11: don?t care (these bits are always 11 when read.) controls ta3ff inversion. 0: disable inversion. 1: enable inversion. selects ta3ff inversion signal. 0: tmra2 1: tmra3 0 inverted by tmra2 1 inverted by tmra3 note: ta3ffcr bits 4, 5, 6 and 7 are undefined when read. figure 3.9.12 tmra registers selects the signal which inverts timer flip-flop 1 (ta1ff). (don?t care unless in 8-bit timer mode) selects the signal which inverts timer flip-flop 3 (ta3ff). (don?t care unless in 8-bit timer mode) ta1ffcr (0xffff_f105) ta3ffcr (0xffff_f10d) tmp1942cy/cz tmp1942cy/cz-179 tmra5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taff5c1 taff5c0 taff5ie taff5is read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert ta5ff value (soft inversion). 01: set ta5ff to 1. 10: clear ta5ff to 0. 11: don?t care (these bits are always 11 when read.) controls ta5ff inversion. 0: disable inversion. 1: enable inversion. selects ta5ff inversion signal. 0: tmra4 1: tmra5 0 inverted by tmra4 1 inverted by tmra5 note: ta5ffcr bits 4, 5, 6 and 7 are undefined when read. tmra7 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taff7c1 taff7c0 taff7ie taff7is read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert ta7ff value (soft inversion). 01: set ta7ff to 1. 10: clear ta7ff to 0. 11: don?t care (these bits are always 11 when read.) controls ta7ff inversion. 0: disable inversion. 1: enable inversion. selects ta7ff inversion signal. 0: tmra6 1: tmra7 0 inverted by tmra6 1 inverted by tmra7 note: ta7ffcr bits 4, 5, 6 and 7 are undefined when read. figure 3.9.13 tmra registers selects the signal which inverts timer flip-flop 5 (ta5ff). (don?t care unless in 8-bit timer mode) selects the signal which inverts timer flip-flop 7 (ta7ff). (don?t care unless in 8-bit timer mode) ta5ffcr (0xffff_f115) ta7ffcr (0xffff_f11d) tmp1942cy/cz tmp1942cy/cz-180 tmra9 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taff9c1 taff9c0 taff9ie taff9is read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert ta9ff value (soft inversion). 01: set ta9ff to 1. 10: clear ta9ff to 0. 11: don?t care (these bits are always 11 when read.) controls ta9ff inversion. 0: disable inversion. 1: enable inversion. selects ta9ff inversion signal. 0: tmra8 1: tmra9 0 inverted by tmra8 1 inverted by tmra9 note: ta9ffcr bits 4, 5, 6 and 7 are undefined when read. tmrab flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? taffbc1 taffbc0 taffbie taffbis read/write ? ? ? ? r/w after reset ? ? ? ? 1 1 0 0 function 00: invert tabff value (soft inversion). 01: set tabff to 1. 10: clear tabff to 0. 11: don?t care (these bits are always 11 when read.) controls tabff inversion. 0: disable inversion. 1: enable inversion. selects tabff inversion signal. 0: tmraa 1: tmrab 0 inverted by tmraa 1 inverted by tmrab note: tabffcr bits 4, 5, 6 and 7 are undefined when read. figure 3.9.14 tmra registers selects the signal which inverts timer flip-flop 9 (ta9ff). (don?t care unless in 8-bit timer mode) selects the signal which inverts timer flip-flop b (tabff). (don?t care unless in 8-bit timer mode) ta9ffcr (0xffff_f125) tabffcr (0xffff_f12d) tmp1942cy/cz tmp1942cy/cz-181 3.9.4 functional description for each mode (1) 8-bit timer mode tmra0 and tmra1 can be used as 8-bit interval timers independently of each other. you must stop tmra0 and tmra1 before attempting to set their functions or count data. a. generating interrupts periodically the following description uses tmra1 as an e ample. to generate a tram1 interrupt, intta1, at certain intervals, first stop timer 1 and set the operating mode, input clock and cycle in the ta01mod and ta1reg registers. ne t, enable the intta1 interrupt and start timer 1. e ample: to generate intta1 interrupts every 20 s with fc = 32 mhz, set the registers in the following sequence: * clock conditions system clock: high-speed (fc) prescaler clock: fperiph/4 (fperiph = fsys) msb lsb 7 6 5 4 3210 ta01run ? ? x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 10xx select 8-bit timer mode and set input clock to t1 (0.25 s resolution, fc = 32 mhz). ta1reg 0 1 0 1 0000 write 20 s/ t1 = 80 (50h) to ta1reg. imc5lh x x 1 1 0101 enable intta1 and set interrupt level = 5 and rising edge detection. ta01run ? x x x ? 11 ? start tmra1. note: x = don?t care; ??? = no change for a description of input clock selection, refer to table 3.9.3. note: the input clocks for tmra0 and tmra1 differ as shown below. tmra0: ta0in pin input, t1, t4 or t16 tmra1: tmra0 match detection signal, t1, t16 or t256 tmp1942cy/cz tmp1942cy/cz-182 b. outputting a 50% duty cycle square wave invert the value of timer flip-flop ta1ff at certain intervals and forward the inverted value to the timer flip-flop output pin, ta1out. e ample: to output a 1.5- s cycle square wave with fc = 32 mhz on the ta1out pin, set each register in the following sequence. in this e ample tmra1 is used to show how to set the registers, although either tmra0 or tmra1 may be used. * clock conditions system clock: high-speed (fc) high-speed clock gear: 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) 7 6 5 4 3210 ta01run ? x x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 0 1 ? ? select 8-bit timer mode and set input clock to t1 (0.25 s resolution, fc = 32 mhz). ta1reg 0 0 0 0 0011 write (1.5 s/ t1)/2 = 3 to ta1reg. ta1ffcr x x x x 1011 clear ta1ff to 0 and set it to be cleared by match detection signal from tmra1. p7cr ? ? ? ? ? ? 1 ? p7fc ? ? ? ? ? ? 1 ? set pa6 to ta1out output pin. ta01run ? x x x ? 11 ? start tmra1. note: x = don?t care; ??? = no change figure 3.9.15 square wave out put timing (50% duty cycle) c. using a match signal from tmra0 to make tmra1 count select 8-bit timer mode and set the tmra1 input clock to the tmra0 comparator output. figure 3.9.16 tmra1 counting based on tmra0 0.75 s @fc = 32 mhz bit7 2 t1 intta1 up-counter clea r ta1ff bit0 bit1 ta01run tmp1942cy/cz tmp1942cy/cz-183 (2) 16-bit timer mode tmra0 and tmra1 can be used together as a 16-bit interval timer. to select 16-bit timer mode, set ta01mod tmp1942cy/cz tmp1942cy/cz-184 (3) 8-bit ppg (programmable square wave) output mode a square wave of any frequency with any duty cycle can be output using tmra0. either low-active or high-active out put pulses can be selected. tmra1 cannot be used in this mode. the square wave is forwarded to ta1out (shared with pa6). figure 3.9.18 8-bit ppg output waveform this mode is used to output a programmable square wave by inverting the timer output every time the 8-bit up-counter uc0 matches the timer registers ta0reg and ta1reg. however, the condition (ta0reg set value) < (ta1reg set value) must be satisfied. although the up-counter uc1 of tmra1 cannot be used in this mode, ta01run tmp1942cy/cz tmp1942cy/cz-185 if ta0reg has its double-buffer enabled in this m ode, the value in the register buffer is shifted into ta0reg when ta1reg and uc0 match. if it is necessary to change the duty cycle, using the double-buffer facilitates satisfying the requirements for small duty cycle waveforms. figure 3.9.20 register buffer operation e ample: to output a 1/4 duty cycl e 50-khz pulse (fc = 32 mhz) * clock conditions system clock: high-speed (fc) high-speed clock gear: 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) calculate the values to be set in the timer registers as follows: to obtain a frequency of 50 khz, generate a waveform with a period t = 1/50 khz = 20 s. when t1 = 0.25 s (at fc = 32 mhz), 20 s/0.25 s = 80 therefore, ta1reg must be set to 80 (= 50h). ne t, to obtain a 1/4 duty cycle, using the formula t 1/4 = 20 s 1/4 = 5 s, 5 s/0.25 s = 20 therefore, ta0reg must be set to 20 (= 14h). 7 6 5 4 3210 ta01run 0 x x x ? 000 stop tmra0 and tmra1 and clear them to 0. ta01mod 1 0 x x xx01 select 8-bit ppg mode and set input clock to t1. ta0reg 0 0 0 1 0100 write 14h. ta1reg 0 1 0 1 0000 write 50h. ta1ffcr x x x x 011x set ta1ff and enable inversion. if these bits are set to 10, lo w-active output waveform will be obtained. p7cr ? ? ? ? ? ? 1 ? p7fc ? ? ? ? ? ? 1 ? set pa6 to ta1out output pin. ta01run 1 x x x ? 111 start tmra0 and tmra1. note: x = don?t care; ??? = no change shift to register buffer ta0reg and up- counter 0 match ta1reg and up- counter 0 match ta0reg (compare value) register buffe r (up-counter = q 1 ) q 1 write to ta0reg (register buffer) (up-counter = q 2 ) q 2 q 2 q 3 20 s tmp1942cy/cz tmp1942cy/cz-186 (4) 8-bit pwm output mode this mode, only available for tmra0, can output pwm pulses with up to 8-bit resolution. pwm output is forwarded to the ta1out pin (shared with pa6). in this mode tmra1 can be used as an 8-bit timer. timer output is inverted when the up-counter uc0 and the value set in the timer register ta0reg match. it is also inverted when a 2 n -1 counter overflow occurs (n = 6, 7 or 8 as specified in ta01mod tmp1942cy/cz tmp1942cy/cz-187 if ta0reg has its double-buffer enabled in this m ode, the value in the register buffer is shifted into ta0reg upon the detection of a 2 n -1 overflow. using the double-buffer facilitates satisfying the requirements for small duty cycle waveforms. figure 3.9.23 register buffer operation e ample: to output the following pwm wavefo rm on the ta1out pin using tmra0 when fc = 32 mhz * clock conditions system clock: high-speed (fc) high-speed clock gear: 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) to achieve a pwm cycle of 31.75 s with t1 = 0.25 s (at fc = 32 mhz), the following equation must be satisfied: 31.75 s/0.25 s = 127 = 2 n -1 therefore, n must be set to 7. since the low-level period is 18 s and t1 = 0.25 s, 18 s/0.25 s = 72 = 48h therefore, ta0reg must be set to 48h. msb lsb 7 6 5 4 3210 ta01run ? x x x ? ? ? 0 stops tmra0 and clear it to 0. ta01mod 1 1 1 0 ? ? 01 select 8-bit pwm mode (cycle = 2 7 -1) and set input clock to t1. ta0reg 0 1 0 0 1000 write 48h. ta1ffcr x x x x 101x clear ta1ff and enable inversion. p7cr ? ? ? ? ? ? 1 ? p7fc ? ? ? ? ? ? 1 ? set pa6 to ta1out output pin. ta01run 1 x x x ? 1 ? 1 start tmra0. note: x = don?t care; ??? = no change q 2 up-counter = q 2 up-counter = q 1 q 1 q 2 q 3 shift to ta0reg ta0reg and up-counter 0 match 2 n -1 overflo w ta0reg (compare value) register buffe r write to ta0reg (register buffer) 18 s 31.75 s tmp1942cy/cz tmp1942cy/cz-188 table 3.9.4 pwm periods @fc = 32 mhz pwm period 2 6 ? 1 2 7 ? 1 2 8 ? 1 peripheral clock selection tmp1942cy/cz tmp1942cy/cz-189 (5) summary of operating mode settings table 3.9.5 summarizes the settings for tmra01 for each mode. t able 3.9.5 regi ster settings for each timer mode register name ta01mod ta1ffcr register field name tx1942cy/cz 3. 3.10 16-bit timers/event counters (tmrbn) the tmp1942 contains fourteen multi-function 16-b it timer/event counter channels (tmrb0-tmrbd). tmrbn can operate in the following four modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable square wave output (ppg) mode ? 2-phase pulse input counter mode (only for tmrb2 and tmrb3) in addition, when used in combination with the capture function, tmrbn can be run in the following modes: ? frequency measurement mode ? pulse width measurement mode ? time difference measurement mode each channel consists primarily of a 16-bit up-counter , two 16-bit timer registers (one with a double-buffer structure), two 16-bit capture register s, two comparators, capture input co ntroller, and a timer flip-flop with accompanying control circuit. timer operating modes an d flip-flops are controlled by eleven registers. all channels tmrb0 to tmrbd oper ate independently of each other. because each channel functions the same way except for the 2-phase pulse counter function and a few other differences as shown in tables 3.10.1 to 3.10.2, operation of the tmrb0 only is described here, with an explanation of the 2-phase pulse counter function for tmrb2 and tmrb3. table 3.10.1 specification differences among the tmrb channels channel specification tmrb0 tmrb1 tmrb2 tmrb3 external clock/ capture trigger input pins tb0in0 (shared with pa0) tb0in1 (shared with pa1) tb1in0 (shared with pa3) tb1in1 (shared with pa4) tb2in0 (shared with pb0) tb2in1 (shared with pb1) tb3in0 (shared with pb3) tb3in1 (shared with pb4) capture trigger timer ta3out ta3out ta3out ta3out external pins timer flip-flop output pin tb0out (shared with pa2) tb1out (shared with pa5) tb2out (shared with pb2) tb3out (shared with pb5) timer run register tb0run (0xffff_f140) tb1run (0 xffff_f150) tb2run (0xffff_f160) tb3run (0xffff_f170) timer mode register tb0mod (0xffff_ f142) tb1mod (0xffff_f152) tb2mod (0xffff_f162) tb3mod (0xffff_f172) timer flip-flop control register tb0ffcr (0xffff_f143) tb1ffcr (0xffff_f153) tb2ffcr(0xffff_f163) tb3ffcr (0xffff_f173) timer registers tb0rg0l (0xffff_f148) tb0rg0h (0xffff_f149) tb0rg1l (0xffff_f14a) tb0rg1h (0xffff_f14b) tb1rg0l (0xffff_f158) tb1rg0h (0xffff_f159) tb1rg1l (0xffff_f15a) tb1rg1h (0xffff_f15b) tb2rg0l (0xffff_f168) tb2rg0h (0xffff_f169) tb2rg1l (0xffff_f16a) tb2rg1h (0xffff_f16b) tb3rg0l (0xffff_f178) tb3rg0h (0xffff_f179) tb3rg1l (0xffff_f17a) tb3rg1h (0xffff_f17b) register name (address) capture registers tb0cp0l (0xffff_f14c) tb0cp0h (0xffff_f14d) tb0cp1l (0xffff_f14e) tb0cp1h (0xffff_f14f) tb1cp0l (0xffff_f15c) tb1cp0h (0xffff_f15d) tb1cp1l (0xffff_f15e) tb1cp1h (0xffff_f15f) tb2cp0l (0xffff_f16c) tb2cp0h (0xffff_f16d) tb2cp1l (0xffff_f16e) tb2cp1h (0xffff_f16f) tb3cp0l (0xffff_f17c) tb3cp0h (0xffff_f17d) tb3cpil (0xffff_f17e) tb3cpih (0xffff_f17f) tmp1942cy/cz-190 tx1942cy/cz table 3.10.2 specification differences among the tmrb channels channel specification tmrb4 tmrb5 tmrb6 tmrb7 external clock/ capture trigger input pins tb4in0 (shared with pb2) tb4in1 (shared with pb5) ? ? tb4in0 (shared with p95) tb4in1 (shared with p96) capture trigger timer ta3out ta3out ta3out ta3out external pins timer flip-flop output pin tb4out (shared with p92) tb5out (shared with p93) tb6out (shared with p94) tb7out (shared with p97) timer run register tb4run (0xffff_f180) tb5run (0 xffff_f190) tb6run (0xffff_f1 a0) tb7run (0xffff_f1b0) timer mode register tb4mod (0xffff_ f182) tb5mod (0xffff_f192) tb6mod (0xffff_f1a2) tb7mod (0xffff_f1b2) timer flip-flop control register tb4ffcr (0xffff_f183) tb5ffcr (0xffff_f193) tb 6ffcr(0xffff_f1a3) tb7ffcr (0xffff_f1b3) timer registers tb4rg0l (0xffff_f188) tb4rg0h (0xffff_f189) tb4rg1l (0xffff_f18a) tb4rg1h (0xffff_f18b) tb5rg0l (0xffff_f198) tb5rg0h (0xffff_f199) tb5rg1l (0xffff_f19a) tb5rg1h (0xffff_f19b) tb6rg0l (0xffff_f1a8) tb6rg0h (0xffff_f1a9) tb6rg1l (0xffff_f1aa) tb6rg1h (0xffff_f1ab) tb7rg0l (0xffff_f1b8) tb7rg0h (0xffff_f1b9) tb7rg1l (0xffff_f1ba) tb7rg1h (0xffff_f1bb) register name (address) capture registers tb4cp0l (0xffff_f18c) tb4cp0h (0xffff_f18d) tb4cp1l (0xffff_f18e) tb4cp1h (0xffff_f18f) tb5cp0l (0xffff_f19c) tb5cp0h (0xffff_f19d) tb5cp1l (0xffff_f19e) tb5cp1h (0xffff_f19f) tb6cp0l(0xffff_f1ac) tb6cp0h(0xffff_f1ad) tb6cp1l (0xffff_f1ae) tb6cp1h (0xffff_f1af) tb7cp0l (0xffff_f1bc) tb7cp0h(0xffff_f1bd) tb7cpil (0xffff_f1be) tb7cpih (0xffff_f1bf) table 3.10.3 specification differences among the tmrb channels channel specification tmrb8 tmrb9 tmrba tmrbb external clock/ capture trigger input pins tb8in0 (shared with pc6) tb8in1 (shared with pc7) tb9in0 (shared with pd0) tb8in1 (shared with pd1) tbain0 (shared with pd5) tbain1 (shared with pd6) ? capture trigger timer ta5out ta5out ta5out ta5out external pins timer flip-flop output pin ? ? ? ? timer run register tb8run (0xffff_ f1c0) tb9run (0xffff_f1d0) tbarun (0 xffff_f1e0) tbbrun (0xffff_f1f0) timer mode register tb8mod (0xffff_f1c2) tb9mod (0x ffff_f1d2) tbamod (0xffff_f1e2) tbbmod (0xffff_f1f2) timer flip-flop control register ? ? ? ? timer registers tb8rg0l (0xffff_f1c8) tb8rg0h (0xffff_f1c9) tb8rg1l (0xffff_f1ca) tb8rg1h (0xffff_f1cb) tb9rg0l (0xffff_f1d8) tb9rg0h (0xffff_f1d9) tb9rg1l (0xffff_f1da) tb9rg1h (0xffff_f1db) tbarg0l (0xffff_f1e8) tbarg0h (0xffff_f1e9) tbarg1l (0xffff_f1ea) tbarg1h (0xffff_f1eb) tbbrg0l (0xffff_f1f8) tbbrg0h (0xffff_f1f9) tbbrg1l (0xffff_f1fa) tbbrg1h (0xffff_f1fb) register name (address) capture registers tb8cp0l (0xffff_f1cc) tb8cp0h (0xffff_f1cd) tb8cp1l (0xffff_f1ce) tb8cp1h (0xffff_f1cf) tb9cp0l (0xffff_f1dc) tb9cp0h (0xffff_f1dd) tb9cp1l (0xffff_f1de) tb9cp1h (0xffff_f1df) tbacp0l (0xffff_f1ec) tbacp0h (0xffff_f1ed) tbacp1l (0xffff_f1ee) tbacp1h (0xffff_f1ef) tbbcp0l (0xffff_f1fc) tbbcp0h (0xffff_f1fd) tbbcpil (0xffff_f1fe) tbbcpih (0xffff_f1ff) tmp1942cy/cz-191 tx1942cy/cz table 3.10.4 specification differences among the tmrb channels channel specification tmrbc tmrbd external clock/ capture trigger input pins capture trigger timer ta5out ta5out external pins timer flip-flop output pin timer run register tbcrun (0xffff_f200) tbdrun (0xffff_f210) timer mode register tbcmod (0xffff_f202) tbdmod (0xffff_f212) timer flip-flop control register timer registers tbcrg0l (0xffff_f208) tbcrg0h (0xffff_f209) tbcrg1l (0xffff_f20a) tbcrg1h (0xffff_f20b) tbdrg0l (0xffff_f218) tbdrg0h (0xffff_f219) tbdrg1l (0xffff_f21a) tbdrg1h (0xffff_f21b) register name (address) capture registers tbccp0l (0xffff_f20c) tbccp0h (0xffff_f20d) tbccp1l (0xffff_f20e) tbccp1h (0xffff_f20f) tbdcp0l (0xffff_f21c) tbdcp0h (0xffff_f21d) tbdcp1l (0xffff_f21e) tbdcp1h (0xffff_f21f) tmp1942cy/cz-192 tx1942cy/cz 3.10.1 block diagrams internal data bus internal data bus run/ clear match detect 16-bit comparator ( cp0 ) 16-bit timer register tb0rg0h/l 16-bit comparator ( cp1 ) register buffer 0 16-bit timer register tb0rg1h/l match detect counter clock tb0mod tx1942cy/cz internal data bus internal data bus run/ clear match detect 16-bit comperator ( cp0 ) 16-bit timer register tb2rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb2rg1h/l match detect count clock tb2mod tx1942cy/cz (2) up-counter (uc0) uc0 is a 16-bit binary counter which counts up synchronously with the input clock selected by tb0mod tx1942cy/cz (4) capture registers (tb0cp0h/l and tb0cp1h/l) tb0cp0h/l and tb0cp1h/l are 16-bit registers used to latch the value of the up-counter uc0. data may be read out from a capture register in a single operation using a 2-byte data transfer instruction, or in two operations (the eight low-order bits first and then the eight high-order bits) using a 1-byte data transfer instruction. (5) capture controller this circuit controls the timing at which the value in the up-counter uc0 is latched into the capture registers (tb0cp0 and tb0cp1). the capture register latch timing is set using tb0mod tx1942cy/cz 3.10.3 register description tmrb0 run register 7 6 5 4 3 2 1 0 bit symbol tb0rde ? ? ? i2tb0 tb0prun ? tb0run read/write r/w r/w ? r/w r/w r/w ? r/w after reset 0 0 ? 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count tb0run (0xffff_ f140) i2tb0: operation in idle mode tb0prun: operation of the prescaler tb0run: operation of timer b0 note: tb0run bits 1 and 5 are undefined when read. tmrb1 run register 7 6 5 4 3 2 1 0 bit symbol tb1rde ? ? ? i2tb1 tb1prun ? tb1run read/write r/w r/w ? r/w r/w r/w ? r/w after reset 0 0 ? 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb1: operation in idle mode tb1prun: operation of the prescaler tb1run: operation of timer b1 note: tb1run bits 1 and 5 are undefined when read. tb1run (0xffff_ f150) figure 3.10.3 tmrb registers tmp1942cy/cz-198 tx1942cy/cz tmrb2 run register 7 6 5 4 3 2 1 0 bit symbol tb2rde ? ud2ck tb2udce i2tb2 tb2prun tb2run read/write r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 function double buffer 0: disable 1: enable must always be set to 0. sampling clock 0: fs 1: fsys/2 2-phase counter enable 0: disable 1: enable idle 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count tb2run (0xffff_ f160) i2tb2: operation in idle mode tb2prun: operation of the prescaler tb2run: operation of timer b2 tb2udce: operation of the 2-phase pulse input counter ud2ck: sampling clock selection for 2-phase pulse input note 1: tb2run bits 1 and 5 are undefined when read. note 2: setting tb2run bit 4 to 1 selects 2-phase pulse input counter mode, causing the counter to operate as an up/down-counter. clearing the bit to 0 restores normal timer mode, causing the timer to operate as an up-counter. tmrb3 run register 7 6 5 4 3 2 1 0 bit symbol tb3rde ? ud3ck tb3udce i2tb3 tb3prun ? tb3run read/write r/w r/w r/w r/w r/w r/w ? r/w after reset 0 0 0 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. sampling clock 0: fs 1: fsys/2 2-phase counter enable 0: disable 1: enable idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb3: operation in idle mode tb3prun: operation of the prescaler tb3run: operation of timer b3 tb3udce: operation of the 2-phase pulse input counter ud3ck: sampling clock selection for 2-phase pulse input note 1: tb3run bits 1 and 5 are undefined when read. note 2: setting tb3run bit 4 to 1 selects 2-phase pulse input counter mode, causing the counter to operate as an up/down-counter. clearing the bit to 0 restores normal timer mode, causing the timer to operate as an up-counter. tb3run (0xffff_ f170) figure 3.10.4 tmrb registers tmp1942cy/cz-199 tx1942cy/cz tmrb4 run register 7 6 5 4 3 2 1 0 bit symbol tb4rde ? ? ? i2tb4 tb4prun ? tb4run read/write r/w r/w ? r/w r/w r/w ? r/w after reset 0 0 ? 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count tb4run (0xffff_ f180) i2tb4: operation in idle mode tb4prun: operation of the prescaler tb4run: operation of timer b4 note: tb4run bits 1 and 5 are undefined when read. tmrb5 run register 7 6 5 4 3 2 1 0 bit symbol tb5rde ? ? ? i2tb5 tb5prun ? tb5run read/write r/w r/w ? r/w r/w r/w ? r/w after reset 0 0 ? 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb5: operation in idle mode tb5prun: operation of the prescaler tb5run: operation of timer b5 note: tb5run bits 1 and 5 are undefined when read. tmrb6 run register 7 6 5 4 3 2 1 0 bit symbol tb6rde ? ? ? i2tb6 tb6prun ? tb6run read/write r/w r/w ? r/w r/w r/w ? r/w after reset 0 0 ? 0 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb6: operation in idle mode tb6prun: operation of the prescaler tb6run: operation of timer b6 note: tb6run bits 1 and 5 are undefined when read. tb5run (0xffff_ f190) tb6run (0xffff_ f1a0) figure 3.10.5 tmrb registers tmp1942cy/cz-200 tx1942cy/cz tmrb7 run register 7 6 5 4 3 2 1 0 bit symbol tb7rde ? ? ? i2tb7 tb7prun ? tb7run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count tb7run (0xffff_ f1b0) i2tb7: operation in idle mode tb7prun: operation of the prescaler tb7run: operation of timer b7 note: tb7run bits 1 and 5 are undefined when read. tmrb8 run register 7 6 5 4 3 2 1 0 bit symbol tb8rde ? ? ? i2tb8 tb8prun ? tb8run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb8: operation in idle mode tb8prun: operation of the prescaler tb8run: operation of timer b8 note: tb8run bits 1 and 5 are undefined when read. tmrb9 run register 7 6 5 4 3 2 1 0 bit symbol tb9rde ? ? ? i2tb9 tb9prun ? tb9run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tb9: operation in idle mode tb9prun: operation of the prescaler tb9run: operation of timer b9 note: tb9run bits 1 and 5 are undefined when read. tb9run (0xffff_ f1d0) tb8run (0xffff_ f1c0) figure 3.10.6 tmrb registers tmp1942cy/cz-201 tx1942cy/cz tmrba run register 7 6 5 4 3 2 1 0 bit symbol tbarde ? ? ? i2tba tbaprun ? tbarun read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count tbarun (0xffff_ f1e0) i2tba: operation in idle mode tbaprun: operation of the prescaler tbarun: operation of timer ba note: tbarun bits 1 and 5 are undefined when read. tmrbb run register 7 6 5 4 3 2 1 0 bit symbol tbbrde ? ? ? i2tbb tbbprun ? tbbrun read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tbb: operation in idle mode tbbprun: operation of the prescaler tbbrun: operation of timer bb note: tbbrun bits 1 and 5 are undefined when read. tmrbc run register 7 6 5 4 3 2 1 0 bit symbol tbcrde ? ? ? i2tbc tbcprun ? tbcrun read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tbc: operation in idle mode tbcprun: operation of the prescaler tbcrun: operation of timer bc note: tbcrun bits 1 and 5 are undefined when read. tbbrun (0xffff_ f1f0) tbcrun (0xffff_ f200) figure 3.10.7 tmrb registers tmp1942cy/cz-202 tx1942cy/cz tmrbd run register 7 6 5 4 3 2 1 0 bit symbol tbdrde ? ? ? i2tbd tbdprun ? tbdrun read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 ? ? 0 0 ? 0 function double buffer 0: disable 1: enable must always be set to 0. must always be set to 0. idle 0: idle 1: operate 16-bit timer run/stop control 0: stop and cleared 1: count i2tbd: operation in idle mode tbdprun: operation of the prescaler tbdrun: operation of timer bd note: tbdrun bits 1 and 5 are undefined when read. tbdrun (0xffff_ f210) figure 3.10.8 tmrb registers tmp1942cy/cz-203 tx1942cy/cz tmp1942cy/cz-204 tmrb0 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb0cp0 tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 read/write ? w r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb0in0 tb0in1 10: tb0in0 tb0in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb0in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb0rg1 capture control 00 capture disabled 01 latches value into tb0cp0 at rise of tb0in0. latches value into tb0cp1 at rise of tb0in1. 10 latches value into tb0cp0 at rise of tb0in0. latches value into tb0cp1 at fall of tb0in0. 11 latches value into tb0cp0 at rise of ta3out. latches value into tb0cp1 at fall of ta3out. 0 latches up-counter value into tb0cp0. 1 don?t care tmrb1 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb1cp0 tb1cpm1 tb1cpm0 tb1cle tb1clk1 tb1clk0 read/write r/w w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb1n0 tb1in1 10: tb1in0 tb1in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb1in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb1rg1 capture control 00 capture disabled 01 latches value into tb1cp0 at rise of tb1in0. latches value into tb1cp1 at rise of tb1in1. 10 latches value into tb1cp0 at rise of tb1in0. latches value into tb1cp1 at fall of tb1in0. 11 latches value into tb1cp0 at rise of ta3out. latches value into tb1cp1 at fall of ta3out. 0 latches up-counter value into tb1cp0. 1 don?t care figure 3.10.9 tmrb registers tb0mod (0xffff_ f142) clearing up-counter (uc0) software capture capture timing tb1mod (0xffff_ f152) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-205 tmrb2 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb2cp0 tb2cpm1 tb2cpm0 tb2cle tb2clk1 tb2clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb2in0 tb2in1 10: tb2in0 tb2in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb2in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb2rg1 capture control 00 capture disabled 01 latches value into tb2cp0 at rise of tb2in0. latches value into tb2cp1 at rise of tb2in1. 10 latches value into tb2cp0 at rise of tb2in0. latches value into tb2cp1 at fall of tb2in0. 11 latches value into tb2cp0 at rise of ta3out. latches value into tb2cp1 at fall of ta3out. 0 latches up-counter value into tb2cp0. 1 don?t care tmrb3 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb3cp0 tb3cpm1 tb3cpm0 tb3cle tb3clk1 tb3clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb3in0 tb3in1 10: tb3in0 tb3in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb3in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb3rg1 capture control 00 capture disabled 01 latches value into tb3cp0 at rise of tb3in0. latches value into tb3cp1 at rise of tb3in1. 10 latches value into tb3cp0 at rise of tb3in0. latches value into tb3cp1 at fall of tb3in0. 11 latches value into tb3cp0 at rise of ta3out. latches value into tb3cp1 at fall of ta3out. 0 latches up-counter value into tb3cp0. 1 don?t care figure 3.10.10 tmrb registers tb2mod (0xffff_ f162) clearing up-counter (uc0) software capture capture timing tb3mod (0xffff_ f172) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-206 tmrb4 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb4cp0 tb4cpm1 tb4cpm0 tb4cle tb4clk1 tb4clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb4in0 tb4in1 10: tb4in0 tb4in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb4in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb4rg1 capture control 00 capture disabled 01 latches value into tb4cp0 at rise of tb4in0. latches value into tb4cp1 at rise of tb4in1. 10 latches value into tb4cp0 at rise of tb4in0. latches value into tb4cp1 at fall of tb4in0. 11 latches value into tb4cp0 at rise of ta3out. latches value into tb4cp1 at fall of ta3out. 0 latches up-counter value into tb4cp0. 1 don?t care tmrb5 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb5cp0 tb5cpm1 tb5cpm0 tb5cle tb5clk1 tb5clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: setting prohibited 10: setting prohibited 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: setting prohibited 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb5rg1 00 capture disabled 01 capture disabled 10 capture disabled 11 latches value into tb5cp0 at rise of ta3out. latches value into tb5cp1 at fall of ta3out. 0 latches up-counter value into tb5cp0. 1 don?t care figure 3.10.11 tmrb registers tb5mod (0xffff_ f192) clearing up-counter (uc0) software capture capture timing tb4mod (0xffff_ f182) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-207 tmrb6 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb6cp0 tb6cpm1 tb6cpm0 tb6cle tb6clk1 tb6clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: setting prohibited 10: setting prohibited 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: setting prohibited 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb6rg1 00 capture disabled 01 capture disabled 10 capture disabled 11 latches value into tb6cp0 at rise of ta3out. latches value into tb6cp1 at fall of ta3out. 0 latches up-counter value into tb6cp0. 1 don?t care tmrb7 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb7cp0 tb7cpm1 tb7cpm0 tb7cle tb7clk1 tb7clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb7in0 tb7in1 10: tb7in0 tb7in0 11: ta3out ta3out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb7in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb7rg1 00 capture disabled 01 latches value into tb7cp0 at rise of tb7in0. latches value into tb7cp1 at rise of tb7in1. 10 latches value into tb7cp0 at rise of tb7in0. latches value into tb7cp1 at fall of tb7in0. 11 latches value into tb7cp0 at rise of ta3out. latches value into tb7cp1 at fall of ta3out. 0 latches up-counter value into tb7cp0. 1 don?t care figure 3.10.12 tmrb registers tb6mod (0xffff_ f1a2) clearing up-counter (uc0) software capture capture timing tb7mod (0xffff_ f1b2) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-208 tmrb8 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb8cp0 tb8cpm1 tb8cpm0 tb8cle tb8clk1 tb8clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb8in0 tb8in1 10: tb8in0 tb8in0 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb8in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb8rg1 00 capture disabled 01 latches value into tb8cp0 at rise of tb8in0. latches value into tb8cp1 at rise of tb8in1. 10 latches value into tb8cp0 at rise of tb8in0. latches value into tb8cp1 at fall of tb8in0. 11 latches value into tb8cp0 at rise of ta5out. latches value into tb8cp1 at fall of ta5out. 0 latches up-counter value into tb8cp0. 1 don?t care tmrb9 mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tb9cp0 tb9cpm1 tb9cpm0 tb9cle tb9clk1 tb9clk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tb9in0 tb9in1 10: tb9in0 tb9in0 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tb9in0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tb9rg1 00 capture disabled 01 latches value into tb9cp0 at rise of tb9in0. latches value into tb9cp1 at rise of tb9in1. 10 latches value into tb9cp0 at rise of tb9in0. latches value into tb9cp1 at fall of tb9in0. 11 latches value into tb9cp0 at rise of ta5out. latches value into tb9cp1 at fall of ta5out. 0 latches up-counter value into tb9cp0. 1 don?t care figure 3.10.13 tmrb registers tb8mod (0xffff_ f1c2) clearing up-counter (uc0) software capture capture timing tb9mod (0xffff_ f1d2) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-209 tmrba mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tbacp0 tbacpm1 tbacpm0 t bacle tbaclk1 tbaclk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: tbain0 tbain1 10: tbain0 tbain0 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: tbain0 pin input 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tbarg1 00 capture disabled 01 latches value into tbacp0 at rise of tbain0. latches value into tbacp1 at rise of tbain1. 10 latches value into tbacp0 at rise of tbain0. latches value into tbacp1 at fall of tbain0. 11 latches value into tbacp0 at rise of ta5out. latches value into tbacp1 at fall of ta5out. 0 latches up-counter value into tbacp0. 1 don?t care tmrbb mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tbbcp0 tbbcpm1 tbbcpm0 t bbcle tbbclk1 tbbclk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: setting prohibited 10: setting prohibited 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: setting prohibited 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tbbrg1 00 capture disabled 01 capture disabled 10 capture disabled 11 latches value into tbbcp0 at rise of ta5out. latches value into tbbcp1 at fall of ta5out. 0 latches up-counter value into tbbcp0. 1 don?t care figure 3.10.14 tmrb registers tbamod (0xffff_ f1e2) clearing up-counter (uc0) software capture capture timing tbbmod (0xffff_ f1f2) clearing up-counter (uc0) software capture capture timing tx1942cy/cz tmp1942cy/cz-210 tmrbc mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tbccp0 tbccpm1 tbccpm0 tbccle tbcclk1 tbcclk0 read/write ? w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: setting prohibited 10: setting prohibited 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: setting prohibited 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tbcrg1 00 capture disabled 01 capture disabled 10 capture disabled 11 latches value into tbccp0 at rise of ta5out. latches value into tbccp1 at fall of ta5out. 0 latches up-counter value into tbccp0. 1 don?t care tmrbd mode register 7 6 5 4 3 2 1 0 bit symbol ? ? tbdcp0 tbdcpm1 tbdcpm0 tbdcle tbdclk1 tbdclk0 read/write w * r/w after reset 0 0 1 0 0 0 0 0 function must always be set to 00. software capture control 0: software capture 1: don?t care capture timing 00: disabled 01: disabled 10: disabled 11: ta5out ta5out up-counter control 0: clearing disabled 1: clearing enabled source clock selection 00: setting prohibited 01: t1 10: t4 11: t16 0 clearing of up-counter disabled 1 up-counter cleared when it matches tbdrg1 00 capture disabled 01 capture disabled 10 capture disabled 11 latches value into tbdcp0 at rise of ta5out. latches value into tbdcp1 at fall of ta5out. 0 latches up-counter value into tbdcp0. 1 don?t care figure 3.10.15 tmrb registers tbcmod (0xffff_ f202) clearing up-counter (uc0) software capture capture timing clearing up-counter (uc0) software capture capture timing tbdmod (0xffff_ f212) tx1942cy/cz tmp1942cy/cz-211 tmrb0 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb0ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb0cp1 when up-counter value is latched into tb0cp0 when up-counter and tb0rg1 values match when up-counter and tb0rg0 values match tb0ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb0ff0 value inverted (soft inversion) 01 tb0ff0 set to 1 10 tb0ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.16 tmrb registers tb0ffcr (0xffff_ f143) control of timer flip-flop (tb0ff0) trigger for inverting timer flip-flop (tb0ff0) when up-counter and tb0rg0 values match trigger for inverting timer flip-flop (tb0ff0) when up-counter and tb0rg1 values match trigger for inverting timer flip-flop (tb0ff0) when up-counter value is latched into tb0cp0 trigger for inverting timer flip-flop (tb0ff0) when up-counter value is latched into tb0cp1 tx1942cy/cz tmp1942cy/cz-212 tmrb1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb1c1t1 tb1c0t1 tb1e1t1 tb1e0t1 tb1ff0c1 tb1ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb1ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb1cp1 when up-counter value is latched into tb1cp0 when up-counter and tb1rg1 values match when up-counter and tb1rg0 values match tb1ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb1ff0 value inverted (soft inversion) 01 tb1ff0 set to 1 10 tb1ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.17 tmrb registers tb1ffcr (0xffff_ f153) control of timer flip-flop (tb1ff0) trigger for inverting timer flip-flop (tb1ff0) when up-counter and tb1rg0 values match trigger for inverting timer flip-flop (tb1ff0) when up-counter and tb1rg1 values match trigger for inverting timer flip-flop (tb1ff0) when up-counter value is latched into tb1cp0 trigger for inverting timer flip-flop (tb1ff0) when up-counter value is latched into tb1cp1 tx1942cy/cz tmp1942cy/cz-213 tmrb2 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb2c1t1 tb2c0t1 tb2e1t1 tb2e0t1 tb2ff0c1 tb2ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb2ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb2cp1 when up-counter value is latched into tb2cp0 when up-counter and tb2rg1 values match when up-counter and tb2rg0 values match tb2ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb2ff0 value inverted (soft inversion) 01 tb2ff0 set to 1 10 tb2ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.18 tmrb registers tb2ffcr (0xffff_ f163) control of timer flip-flop (tb2ff0) trigger for inverting timer flip-flop (tb2ff0) when up-counter and tb2rg0 values match trigger for inverting timer flip-flop (tb2ff0) when up-counter and tb2rg1 values match trigger for inverting timer flip-flop (tb2ff0) when up-counter value is latched into tb2cp0 trigger for inverting timer flip-flop (tb2ff0) when up-counter value is latched into tb2cp1 tx1942cy/cz tmp1942cy/cz-214 tmrb3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb3c1t1 tb3c0t1 tb3e1t1 tb3e0t1 tb3ff0c1 tb3ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb3ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb3cp1 when up-counter value is latched into tb3cp0 when up-counter and tb3rg1 values match when up-counter and tb3rg0 values match tb3ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb3ff0 value inverted (soft inversion) 01 tb3ff0 set to 1 10 tb3ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.19 tmrb registers tb3ffcr (0xffff_ f173) control of timer flip-flop (tb3ff0) trigger for inverting timer flip-flop (tb3ff0) when up-counter and tb3rg0 values match trigger for inverting timer flip-flop (tb3ff0) when up-counter and tb3rg1 values match trigger for inverting timer flip-flop (tb3ff0) when up-counter value is latched into tb3cp0 trigger for inverting timer flip-flop (tb3ff0) when up-counter value is latched into tb3cp1 tx1942cy/cz tmp1942cy/cz-215 tmrb4 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb4c1t1 tb4c0t1 tb4e1t1 tb4e0t1 tb4ff0c1 tb4ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb4ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb4cp1 when up-counter value is latched into tb4cp0 when up-counter and tb4rg1 values match when up-counter and tb4rg0 values match tb4ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb4ff0 value inverted (soft inversion) 01 tb4ff0 set to 1 10 tb4ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.20 tmrb registers tb4ffcr (0xffff_ f183) control of timer flip-flop (tb4ff0) trigger for inverting timer flip-flop (tb4ff0) when up-counter and tb4rg0 values match trigger for inverting timer flip-flop (tb4ff0) when up-counter and tb4rg1 values match trigger for inverting timer flip-flop (tb4ff0) when up-counter value is latched into tb4cp0 trigger for inverting timer flip-flop (tb4ff0) when up-counter value is latched into tb4cp1 tx1942cy/cz tmp1942cy/cz-216 tmrb5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb5c1t1 tb5c0t1 tb5e1t1 tb5e0t1 tb5ff0c1 tb5ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb5ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb5cp1 when up-counter value is latched into tb5cp0 when up-counter and tb5rg1 values match when up-counter and tb5rg0 values match tb5ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb5ff0 value inverted (soft inversion) 01 tb5ff0 set to 1 10 tb5ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.21 tmrb registers tb5ffcr (0xffff_ f193) control of timer flip-flop (tb5ff0) trigger for inverting timer flip-flop (tb5ff0) when up-counter and tb5rg0 values match trigger for inverting timer flip-flop (tb5ff0) when up-counter and tb5rg1 values match trigger for inverting timer flip-flop (tb5ff0) when up-counter value is latched into tb5cp0 trigger for inverting timer flip-flop (tb5ff0) when up-counter value is latched into tb5cp1 tx1942cy/cz tmp1942cy/cz-217 tmrb6 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb6c1t1 tb6c0t1 tb6e1t1 tb6e0t1 tb6ff0c1 tb6ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb6ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb6cp1 when up-counter value is latched into tb6cp0 when up-counter and tb6rg1 values match when up-counter and tb6rg0 values match tb6ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb6ff0 value inverted (soft inversion) 01 tb6ff0 set to 1 10 tb6ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.22 tmrb registers tb6ffcr (0xffff_ f1a3) control of timer flip-flop (tb6ff0) trigger for inverting timer flip-flop (tb6ff0) when up-counter and tb6rg0 values match trigger for inverting timer flip-flop (tb6ff0) when up-counter and tb6rg1 values match trigger for inverting timer flip-flop (tb6ff0) when up-counter value is latched into tb6cp0 trigger for inverting timer flip-flop (tb6ff0) when up-counter value is latched into tb6cp1 tx1942cy/cz tmp1942cy/cz-218 tmrb7 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ? ? tb7c1t1 tb7c0t1 tb7e1t1 t b7e0t1 tb7ff0c1 tb7ff0c0 read/write w * r/w w * after reset 1 1 0 0 0 0 1 1 tb7ff0 inversion trigger 0: trigger disabled 1: trigger enabled function must always be set to 11. * these bits are always 11 when read. when up-counter value is latched into tb7cp1 when up-counter value is latched into tb7cp0 when up-counter and tb7rg1 values match when up-counter and tb7rg0 values match tb7ff0 control 00: invert 01: set 10: clear 11: don?t care * these bits are always 11 when read. 00 tb7ff0 value inverted (soft inversion) 01 tb7ff0 set to 1 10 tb7ff0 set to 0 11 don?t care (read as 11) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) 0 trigger disabled (inversion disabled) 1 trigger enabled (inversion enabled) figure 3.10.23 tmrb registers tb7ffcr (0xffff_ f1b3) control of timer flip-flop (tb7ff0) trigger for inverting timer flip-flop (tb7ff0) when up-counter and tb7rg0 values match trigger for inverting timer flip-flop (tb7ff0) when up-counter and tb7rg1 values match trigger for inverting timer flip-flop (tb7ff0) when up-counter value is latched into tb7cp0 trigger for inverting timer flip-flop (tb7ff0) when up-counter value is latched into tb7cp1 tx1942cy/cz tmrb0 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof0 inttb01 inttb00 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb0st (0xffff_ f144) inttb00: interrupt generated upon detection of match with timer register tb0rg0 inttb01: interrupt generated upon detection of match with timer register tb0rg1 inttbof0: interrupt generated upon detection of up-counter overflow tmrb1 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof1 inttb11 inttb10 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb1st (0xffff_ f154) inttb10: interrupt generated upon detection of match with timer register tb1rg0 inttb11: interrupt generated upon detection of match with timer register tb1rg1 inttbof1: interrupt generated upon detection of up-counter overflow figure 3.10.1 tmrb registers tmp1942cy/cz-219 tx1942cy/cz tmrb2 status register a. when tb2run tx1942cy/cz tmrb3 status register a. when tb3run tx1942cy/cz tmrb5 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof4 inttb41 inttb40 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb5st (0xffff_ f194) inttb50: interrupt generated upon detection of match with timer register tb5rg0 inttb51: interrupt generated upon detection of match with timer register tb5rg1 inttbof5: interrupt generated upon detection of up-counter overflow tmrb6 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof6 inttb61 inttb60 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb6st (0xffff_ f1a4) inttb60: interrupt generated upon detection of match with timer register tb6rg0 inttb61: interrupt generated upon detection of match with timer register tb6rg1 inttbof6: interrupt generated upon detection of up-counter overflow tmrb7 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof7 inttb71 inttb70 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb7st (0xffff_ f1b4) inttb70: interrupt generated upon detection of match with timer register tb7rg0 inttb71: interrupt generated upon detection of match with timer register tb7rg1 inttbof7: interrupt generated upon detection of up-counter overflow figure 3.10.27 tmrb registers tmp1942cy/cz-222 tx1942cy/cz tmrb8 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof8 inttb81 inttb80 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb8st (0xffff_ f1c4) inttb80: interrupt generated upon detection of match with timer register tb8rg0 inttb81: interrupt generated upon detection of match with timer register tb8rg1 inttbof8: interrupt generated upon detection of up-counter overflow tmrb9 status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof9 inttb91 inttb90 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tb9st (0xffff_ f1d4) inttb90: interrupt generated upon detection of match with timer register tb9rg0 inttb91: interrupt generated upon detection of match with timer register tb9rg1 inttbof9: interrupt generated upon detection of up-counter overflow tmrba status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbofa inttba1 inttba0 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tbast (0xffff_ f1e4) inttba0: interrupt generated upon detection of match with timer register tbarg0 inttba1: interrupt generated upon detection of match with timer register tbarg1 inttbofa: interrupt generated upon detection of up-counter overflow figure 3.10.28 tmrb registers tmp1942cy/cz-223 tx1942cy/cz tmrbb status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbofb inttbb1 inttbb0 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tbbst (0xffff_ f1f4) inttbb0: interrupt generated upon detection of match with timer register tbbrg0 inttbb1: interrupt generated upon detection of match with timer register tbbrg1 inttbofb: interrupt generated upon detection of up-counter overflow tmrbc status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbof9 inttb91 inttb90 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tbcst (0xffff_ f204) inttbc0: interrupt generated upon detection of match with timer register tbcrg0 inttbc1: interrupt generated upon detection of match with timer register tbcrg1 inttbofc: interrupt generated upon detection of up-counter overflow tmrbd status register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? inttbofd inttbd1 inttbd0 read/write ? ? ? ? ? r after reset ? ? ? ? ? 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tbdst (0xffff_ f214) inttbd0: interrupt generated upon detection of match with timer register tbdrg0 inttbd1: interrupt generated upon detection of match with timer register tbdrg1 inttbofd: interrupt generated upon detection of up-counter overflow figure 3.10.29 tmrb registers tmp1942cy/cz-224 tx1942cy/cz 3.10.4 functional description for each mode (1) 16-bit interval timer mode to generate interrupts at certain intervals, set th e interval time in the timer register tb0rg1 and enable inttb01 interrupts. 7 6 5 4 3210 tb0run 0 0 x x ? 0x0 stop tmrb0. imc7lh x x 1 1 0100 enable inttb0 and set its priority level to 4. tb0ffcr 1 1 0 0 0011 disable trigger. tb0mod 0 0 1 0 0 1 * * ( ** = 01, 10, 11) select prescaler output clock as input clock and disable capture function. tb0rg1 * * * * * * * * set interval time. * * * * * * * * (16 bits) tb0run 0 0 x x ? 1x1 start tmrb0. note: x = don?t care; ??? = no change (2) 16-bit event counter mode the timer can be used as an event counter by selecting an external clock (input to the tb0in0 pin) as its input clock. the up-counter is incremented on each rising edge of the tb0in0 pin input. the count value can be read by capturing it by software and reading the captured value. 7 6 5 4 3210 tb0run 0 0 x x ? 0x0 stop tmrb0. pacr ? ? ? - ? ? ? 0 pafc ? ? ? - ? ? ? 1 set pa0 to input mode. imc7lh x x 1 1 0100 enable inttb0 and set its priority level to 4. tb0ffcr 1 1 0 0 0011 disable trigger. tb0mod 0 0 1 0 0100 select tb0in0 pin input as input clock. tb0rg1 * * * * * * * * set count (16 bits). tb0run 0 0 x x ? 1x1 start tmrb0. note: x = don?t care; ??? = no change when the timer is used as an event counter, the prescaler must be set to run (i.e. tb0run tx1942cy/cz tmp1942cy/cz-226 (3) 16-bit ppg (programmable square wave) output mode a square wave of any frequency with any duty cycle (programmable square wave) can be output. either low-active or high-active output pulses can be selected. this mode is used to output a programmable square wave on the tb0out pin by triggering inversion of the timer flip-flop (tb0ff) when the values in the up-counter (uc0) and one of the timer registers (tb0rg0 or tb0rg1) match. however, the values set in tb0rg0 and tb0rg1 must satisfy the following condition: (tb0rg0 set value) < (tb0rg1 set value) figure 3.10.30 example ppg output waveform if tb0rg0 has its double-buffer enabled in this mode , the value in register buffer 0 is shifted into tb0rg0 when tb0rg1 and uc0 match. using the double-buffer facilitates satisfying the requirements for small duty cycle waveforms. figure 3.10.31 register buffer operation tb0rg0 and up-counter match (inttb00 interrupt) tb0rg1 and up-counter match (inttb01 interrupt) tb0out pin q 1 q 2 q 2 q 3 shift to tb0rg0 up-counter = q 1 up-counter = q 2 tb0rg0 and up-counter match tb0rg1 and up-counter match tb0rg0 (compare value) register buffer write to tb0rg0 tx1942cy/cz tmp1942cy/cz-227 figure 3.10. figure 3.10.32 16-bit ppg output mode block diagram 32 shows a block diagram of 16-bit ppg output mode. to use the timer in 16-bit ppg output m ode, set each register as shown below. 7 6 5 4 3 2 1 0 tb0run 0 0 x x ? 0x0 disable tb0rg0 double-buffer and stop tmrb0. tb0rg0 * * * * * * * * set duty cycle (16 bits). tb0rg1 * * * * * * * * set ppg cycle (16 bits). tb0run 1 0 x x ? 0x0 enable tb0rg0 double-buffer. (duty cycle and ppg cycle are changed by inttb01 interrupt.) tb0ffcr x x 0 0 1 1 1 0 set tb0ff0 so that its value will be inverted on detecting a match with tb0rg0 or tb0rg1. also initialize tb0ff0 to 0. tb0mod 0 0 1 0 0 1 * * ( ** = 01, 10, 11) select prescaler output clock as input clock and disable capture function. p7cr ? 1 ? ? ? ? ? ? p7fc ? 1 ? ? ? ? ? ? set pa2 pin to tb0out. tb0run 1 0 x x ? 1x1 start tmrb0. note1: x = don?t care; ??? = no change note2: please do not stop a timer in ppg mode at the time of duty change (please use a double buffer). in order to change a timer-related setup, please perform the following setup, when you resume after a stop ( tx1942cy/cz tmp1942cy/cz-228 (4) application examples using the capture function with its capture function enabled, tmrb can be used for various applications including those presented in the examples given below: a. one-shot pulse output using an external trigger pulse b. frequency measurement c. pulse width measurement d. time difference measurement a. one-shot pulse output using an external trigger pulse to output a one-shot pulse using an external trigger pulse, follow the procedure described below. let the 16-bit up-counter uc0 count up in free-running mode using the prescaler output clock. enter an external trigger pulse via the tb0in0 pin and use the capture function to latch the up-counter value into the capture register (tb0cp0) at the rising edge of the external trigger pulse. set intc so that an int3 interrupt is generated when the external trigger pulse goes high. during this interrupt write the sum of the tb0cp0 value (c) and the delay time (d) to the timer register tb0rg0. similarly, write the sum of the tb0rg0 value and the one-shot pulse width (p), i.e. (c + d + p), to the timer register tb0rg1. then, set the relevant field in the timer flip-flop control register (tb0ffcr tx1942cy/cz set-up example: to output a 2 ms one-shot pulse with a delay time of 3 ms after an external trigger pulse on the tb0in0 pin * clock conditions system clock: high-speed (fc) high-speed clock gear: 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) settings in the main routine place counter in free-running mode. 7 6 5 4 3210 use t1 as clock source for counting. tb0mod x x 1 0 1001 latch count into tb0cp0 on rise of tb0in0 input. tb0ffcr x x 0 0 0010 clear tb0ff0 to 0. disable inversion of tb0ff0. pacr ? - ? ? ? 1 ? ? pafc ? - ? ? ? 1 ? ? set pa2 pin to tb0out. imc0hl x x 1 1 0100 imc7lh x x 1 1 0000 enable int3 and disable inttb0 tb0run ? 0 x x ? 1x1 start tmrb0. settings in int3 tb0rg0 tb0cp0 + 3ms/ t1 tb0rg1 tb0rg0 + 2ms/ t1 tb0ffcr x x ? ? 11? ? enable tb0ff0 inversion when up-counter value matches tb0rg0 or tb0rg1. imc7lh x x 1 1 0100 enable inttb0. settings in inttb0 tb0ffcr x x ? ? 00? ? disable tb0ff0 inversion when up-counter value matches tb0rg0 or tb0rg1. imc7lh x x 1 1 0000 disable inttb0. note: x = don?t care; ??? = no change if a delay is not necessary, invert tb0ff0 by latching the counter value into tb0cp0; then, during the int3 interrupt, write the sum of the tb0cp0 value (c) and the one-shot pulse width (p) to tb0rg1. enable the trigger so that tb0ff0 will be inverted on detection of a match between the value of uc0 and the value of tb0rg1. tb0ff0 inversion should be disabled during inttb0 interrupt handling. tmp1942cy/cz-229 tx1942cy/cz c + p c inversion enabled (p) pulse width latched into capture register tb0cp0 count clock (prescaler output clock) tb0in0 pin input (external trigger pulse) tb0rg1 and uc0 match tb0out timer output pin latched into capture register tb0cp1 inttb01 generated inversion by latch into tb0cp0 remains enabled tb0ff0 left disabled so that it will not be inverted by latch into tb0cp1 int5 generated figure 3.10.34 one-shot pulse output using an external trigger pulse (without delay) b. frequency measurement with its capture function enabled, the timer can be used to measure the frequency of an external clock. the frequency is measured using a combinati on of a 16-bit timer/event counter and 8-bit timers (tmra01). (tmra01 determines the measurement time by inverting ta1ff.) select tb0in0 pin input as the count clock for tmrb0 so that it counts up synchronously with the external clock pulses. set tb0mod tx1942cy/cz c. pulse width measurement with its capture function enabled, the timer can be used to measure the high-level duration of an external pulse. enter an ex ternal pulse via the tb0in0 pin and let the up-counter (uc0) count up in free-running mode using the prescaler output clock. then, using the capture function, latch the up-counter value into the capture registers tb0cp0 and tb0cp1 on the rising and falling edges of the external pulse, re spectively. set intc so that int5 is generated when the tb0in0 pin goes low. the high-level duration of the pulse can be obtained by finding the difference between tb0cp0 and tb0cp1 and multiplying the resulting value by the internal clock period. for example, if the difference between tb0cp0 and tb0cp1 is 100 and the prescaler output clock period is 0.5 s, then the pulse width will be 100 0.5 s = 50 s. additionally, the pulse width which exceeds the uc0 maximum count time specified by the clock source can be measured by software coding. c2 c1 c2 c1 c2 c1 prescaler output clock tb0in0 pin input (external pulse) latched into tb0cp0 int5 latched into tb0cp1 figure 3.10.36 pulse width measurement figure 3.10. the low-level duration can be measured usin g the time difference measurement function shown in . the low-level duration is obtained by multiplying the difference between the first c2 and the second c1 by the prescaler output clock period during the handling of the second int5 interrupt. tmp1942cy/cz-231 tx1942cy/cz d. time difference measurement with its capture function enabled, the timer can be used to measure the difference in time between two events. let the up-counter (uc0) count up in free-running mode using the prescaler output clock. latch the uc0 value into the capture register tb0cp0 at the rising edge of the pulse input on the tb0in0 pin. set intc so that an int3 interrupt is generated at that point. latch the uc0 value into the capture register (t b0cp1) at the rising e dge of the pulse input on the tb0in1 pin. set intc so that an in t4 interrupt is generated at that point. the difference in time can be obtained by subtracting the value in tb0cp0 from the value in tb0cp1 after the values have been latched into the capture registers, and then multiplying the difference by the internal clock period. time difference c2 c1 tb0in0 pin input tb0in1 pin input int3 latched into tb0cp0 int4 latched into tb0cp1 prescaler output clock figure 3.10.37 time difference measurement tmp1942cy/cz-232 tx1942cy/cz tmp1942cy/cz-233 (5) 2-phase pulse input counter mode (tmrb2 and tmrb3) (the function operates in the same way for tmrb2 and tmrb3. only tmrb2 is described here.) in this mode, the counter is e ither incremented or decremente d by one according to the state transition of 2-phase clock pulses, with a phase difference of 90 degrees, input from tb2in0 and tb2in1. an interrupt is generated when the up/down-counter overflows or underflows, or when it is incremented or decremented. a. count operation ? counting up figure 3.10.38 counting up ? counting down figure 3.10.39 counting down ? sampling clock tmrb2 run register (tb2run) 7 6 5 4 3 2 1 0 bit symbol tb2rde ? ud2ck tb2udce i2tb2 tb2prun ? tb2run read/write r/w ? r/w r/w r/w r/w ? r/w after reset 0 ? 0 0 0 0 ? 0 function double buffer 0: disable 1: enable sampling clock selection 0: fs 1: fsys/2 2-phase counter enable 0: disable 1: enable idle 0: idle 1: operate timer run/stop control 0: stop and cleared 1: count figure 3.10.40 register for setting 2-phase pulse input counter mode 1 1 counter value + 1 tb0in0 tb0in1 01 n n + 1 counter value counter value ? 1 tb0in0 tb0in1 0 1 n n ? 1 counter value 1 0 tx1942cy/cz tmp1942cy/cz-234 bit 5 of the tb2run register (ud2ck) determines the sampling clock to be used. ud2ck (sampling clock selection) = 0: selects fs (32 khz) (8 khz sampling) 1: selects fsys/2 (fsys/8 hz sampling) 1) exiting from stop mode because an 2-phase timer interrupt cannot be used to terminate stop mode, an interrupt on the intb or intc shared pin is used to terminate stop mode. the 2-phase counter enters stop mode while reta ining its previous state. therefore, if the relationship between the state of the input used to terminate stop mode and the retained state satisfies the condition for counting up or dow n, the counter value is incremented or decremented after stop mode has been terminated. (the counter value remains unchanged if the condition is not satisfied.) if it is necessary to obtain a constant counter state after exiting from stop mode, initialize the 2-phase counter after stop mode is terminated (clearing tb2run tx1942cy/cz ? in up/down-counter mode, ordinary intb to inte interrupts (interrupts other than those used to terminate stop/sleep mode) cannot be used. ? the input clock signals are sampled at fs (32 khz) or based on the high-speed clock (system clock). when fs is used, the maximum input frequency is 8 khz. when the high-speed clock is used, the maximum input frequency is fsys/8 hz. setting the up/down-counter set tb2mod tx1942cy/cz tmp1942cy/cz-236 ? in sleep mode the 2-phase pulse input counter operates. enable the intbcde release input in the clock generator (cg). use intnst of the intbcde circ uit to set the active le vel for each interrupt input. an up or down counter input generates an intb or intc interrupt, causing the counter to exit from sleep mode. the interrupt source is determined by reading the flag register intflg. the flag is cleared when read. whethe r this releasing interrupt source causes the counter to count up or down depends on whether the state of the releasing input satisfies the condition for counting up or down. 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? intes intds intcs intbs read/write ? ? ? ? r after reset ? ? ? ? 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated figure 3.10.43 intflg register ? in stop mode the 2-phase pulse input counter stops. enable the intbcde release input in the clock generator (cg). an up or down counter input generates an intb or intc interrupt, causing the counter to exit from stop mode. whether this releasing input causes the counter to count up or down depends on the relationship between the input state prior to entering stop mode and the state of the releasing input. after the releasing input is asserted, the devi ce warms up for the specified period before entering normal or slow mode to restart counting. d. up/down-counter when 2-phase input counter mode is selected (tb2run tmp1942cy/cz tmp1942cy/cz-237 3.11 serial channels (sio) the tmp1942 contains five serial input/output channels: sio0, sio1, sio3, sio4 and sio5. each channel can be operated in (asynchronous) uart mode or (synchronous) i/o interface mode, as shown below. ? i/o interface mode mode 0: transmit and receive i/o data using the sync signal (sclk) for extended i/o operation. mode 1: transmit and receive 7-bit data. ? asynchronous (uart) m ode mode 2: transmit and receive 8-bit data. mode 3: transmit and receive 9-bit data. in modes 1 and 2 a parity bit can be added. mode 3 supports a wake-up function which is used by the master controller in a multi-controller system to initiate communi cation with a slave controller via a serial link. figure 3.11.2 shows a block diagram for sio0. each channel consists of a prescaler, a serial clock generator, a receive buffer and its accompanying control circuit, and a transmit buffer and its accompanying contro l circuit. all channels op erate independently of each other. because all channels operate in the same way, this section consists only of an explanation for sio0. ? mode 0 (i/o interface mode): lsb first ? mode 0 (i/o interface mode): msb first ? mode 1 (7-bit uart mode) ? mode 2 (8-bit uart mode) ? mode 3 (9-bit uart mode) figure 3.11.1 data formats bit 0 1 2 3 4 5 6 start 8 7 stop bit 0 1 2 3 4 5 6 start stop (wake-up) bit 8 7 a ddress (selection code) when bit 8 = 1 data when bit 8 = 0 direction of transfer 7 bit 0 1 2 3 4 5 6 direction of transfer 0 bit 7 6 5 4 3 2 1 bit 0 1 2 3 4 5 6 start stop without parity bit 0 1 2 3 4 5 6 start stop parity with parity bit 0 1 2 3 4 5 6 start stop 7 without parity bit 0 1 2 3 4 5 6 start stop parity 7 with parity tmp1942cy/cz tmp1942cy/cz-238 3.11.1 block diagram (for channel 0 as an example) figure 3.11.2 sio0 block diagram interrupt request intrx0 sc0mod0 tmp1942cy/cz tmp1942cy/cz-239 3.11.2 functional description of each circuit (for channel 0 as an example) (1) prescaler the tmp1942 has a 6-bit prescaler to supply an operating clock to sio0. the prescaler?s input clock t0 has a frequency of fperiph, fperiph/2 or fperiph/4 as selected by syscr0 tmp1942cy/cz tmp1942cy/cz-240 (2) baud rate the baud rate generator is used to generate the transmit/receive clock which determines the rate at which data is transferred via serial channels. the clock source fed to the baud rate generator is the clock t0, t2, t8 or t32 as output by the 6-bit prescaler. this input clock is selected by setting the bits br0cr to specify the rate of transfer. ? for uart mode 1) when br0cr |